| Message ID | 27d2c59cc9a916754e0dc68f44447ecefe378410.1655028401.git.baruch@tkos.co.il (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: IPQ6018 platform support | expand |
On Sun, Jun 12, 2022 at 01:18:34PM +0300, Baruch Siach wrote: > From: Baruch Siach <baruch.siach@siklu.com> > > The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use > PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better > describe its meaning. > > Signed-off-by: Baruch Siach <baruch.siach@siklu.com> > --- > v7: > Use FIELD_PREP for power limit and stale (Pali Rohár) > --- > drivers/pci/controller/dwc/pcie-qcom.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) Reviewed-by: Rob Herring <robh@kernel.org>
On 6/12/22 13:18, Baruch Siach wrote: > From: Baruch Siach <baruch.siach@siklu.com> > > The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use > PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better > describe its meaning. > > Signed-off-by: Baruch Siach <baruch.siach@siklu.com> > --- > v7: > Use FIELD_PREP for power limit and stale (Pali Rohár) > --- > drivers/pci/controller/dwc/pcie-qcom.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2ea13750b492..5ad9be6372f4 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -69,7 +69,20 @@ #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c #define CFG_BRIDGE_SB_INIT BIT(0) -#define PCIE_CAP_LINK1_VAL 0x2FD7F +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \ + 250) +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \ + 1) +#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ + PCI_EXP_SLTCAP_PCP | \ + PCI_EXP_SLTCAP_MRLSP | \ + PCI_EXP_SLTCAP_AIP | \ + PCI_EXP_SLTCAP_PIP | \ + PCI_EXP_SLTCAP_HPS | \ + PCI_EXP_SLTCAP_HPC | \ + PCI_EXP_SLTCAP_EIP | \ + PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ + PCIE_CAP_SLOT_POWER_LIMIT_SCALE) #define PCIE20_PARF_Q2A_FLUSH 0x1AC @@ -1114,7 +1127,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); - writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); val &= ~PCI_EXP_LNKCAP_ASPMS;