| Message ID | 2afedb941294af7ba0658496b4aca3759a4e43ff.1561659046.git.saiprakash.ranjan@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | coresight: Do not default to CPU0 for missing CPU phandle | expand |
Hi Greg, On Thu, 27 Jun 2019 at 12:15, Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> wrote: > > Do not assume the affinity to CPU0 if cpu phandle is omitted. > Update the DT binding rules to reflect the same by changing it > to a required property. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> I'm all good with this patch - can you pick this up for the coming merge window? If not I'll simply keep it in my tree for 5.4. Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > --- > .../devicetree/bindings/arm/coresight-cpu-debug.txt | 4 ++-- > Documentation/devicetree/bindings/arm/coresight.txt | 8 +++++--- > 2 files changed, 7 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > index 298291211ea4..f1de3247c1b7 100644 > --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > @@ -26,8 +26,8 @@ Required properties: > processor core is clocked by the internal CPU clock, so it > is enabled with CPU clock by default. > > -- cpu : the CPU phandle the debug module is affined to. When omitted > - the module is considered to belong to CPU0. > +- cpu : the CPU phandle the debug module is affined to. Do not assume it > + to default to CPU0 if omitted. > > Optional properties: > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index 8a88ddebc1a2..fcc3bacfd8bc 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -59,6 +59,11 @@ its hardware characteristcs. > > * port or ports: see "Graph bindings for Coresight" below. > > +* Additional required property for Embedded Trace Macrocell (version 3.x and > + version 4.x): > + * cpu: the cpu phandle this ETM/PTM is affined to. Do not > + assume it to default to CPU0 if omitted. > + > * Additional required properties for System Trace Macrocells (STM): > * reg: along with the physical base address and length of the register > set as described above, another entry is required to describe the > @@ -87,9 +92,6 @@ its hardware characteristcs. > * arm,cp14: must be present if the system accesses ETM/PTM management > registers via co-processor 14. > > - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the > - source is considered to belong to CPU0. > - > * Optional property for TMC: > > * arm,buffer-size: size of contiguous buffer space for TMC ETR > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >
On 7/4/2019 1:32 AM, Mathieu Poirier wrote: > Hi Greg, > > On Thu, 27 Jun 2019 at 12:15, Sai Prakash Ranjan > <saiprakash.ranjan@codeaurora.org> wrote: >> >> Do not assume the affinity to CPU0 if cpu phandle is omitted. >> Update the DT binding rules to reflect the same by changing it >> to a required property. >> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > > I'm all good with this patch - can you pick this up for the coming > merge window? If not I'll simply keep it in my tree for 5.4. > > Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > I think you missed adding Greg, adding him now ;) -Sai
On Thu, Jul 04, 2019 at 12:13:40PM +0530, Sai Prakash Ranjan wrote: > On 7/4/2019 1:32 AM, Mathieu Poirier wrote: > > Hi Greg, > > > > On Thu, 27 Jun 2019 at 12:15, Sai Prakash Ranjan > > <saiprakash.ranjan@codeaurora.org> wrote: > > > > > > Do not assume the affinity to CPU0 if cpu phandle is omitted. > > > Update the DT binding rules to reflect the same by changing it > > > to a required property. > > > > > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > > > > I'm all good with this patch - can you pick this up for the coming > > merge window? If not I'll simply keep it in my tree for 5.4. > > > > Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> > > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > > > > I think you missed adding Greg, adding him now ;) I don't see any patch here for me to actually take :(
[ Trimming recipients list ] On 04/07/2019 09:02, Greg Kroah-Hartman wrote: > On Thu, Jul 04, 2019 at 12:13:40PM +0530, Sai Prakash Ranjan wrote: > >> On 7/4/2019 1:32 AM, Mathieu Poirier wrote: >> >>> Hi Greg, >>> >>> On Thu, 27 Jun 2019 at 12:15, Sai Prakash Ranjan wrote: >>>> >>>> Do not assume the affinity to CPU0 if cpu phandle is omitted. >>>> Update the DT binding rules to reflect the same by changing it >>>> to a required property. >>>> >>>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >>>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> >>> >>> I'm all good with this patch - can you pick this up for the coming >>> merge window? If not I'll simply keep it in my tree for 5.4. >>> >>> Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> >>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> >> >> I think you missed adding Greg, adding him now ;) > > I don't see any patch here for me to actually take :( I see what you're doing here ^_^ https://lore.kernel.org/patchwork/patch/1094935/ Regards.
On Thu, Jul 04, 2019 at 10:08:24AM +0200, Marc Gonzalez wrote: > [ Trimming recipients list ] > > On 04/07/2019 09:02, Greg Kroah-Hartman wrote: > > > On Thu, Jul 04, 2019 at 12:13:40PM +0530, Sai Prakash Ranjan wrote: > > > >> On 7/4/2019 1:32 AM, Mathieu Poirier wrote: > >> > >>> Hi Greg, > >>> > >>> On Thu, 27 Jun 2019 at 12:15, Sai Prakash Ranjan wrote: > >>>> > >>>> Do not assume the affinity to CPU0 if cpu phandle is omitted. > >>>> Update the DT binding rules to reflect the same by changing it > >>>> to a required property. > >>>> > >>>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > >>>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > >>> > >>> I'm all good with this patch - can you pick this up for the coming > >>> merge window? If not I'll simply keep it in my tree for 5.4. > >>> > >>> Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> > >>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > >> > >> I think you missed adding Greg, adding him now ;) > > > > I don't see any patch here for me to actually take :( > > I see what you're doing here ^_^ > > https://lore.kernel.org/patchwork/patch/1094935/ What can I do with a random url? Please send patches as emails, if you want me to be able to actually take it. greg k-h
On 7/4/2019 1:48 PM, Greg Kroah-Hartman wrote: > On Thu, Jul 04, 2019 at 10:08:24AM +0200, Marc Gonzalez wrote: >> [ Trimming recipients list ] >> >> On 04/07/2019 09:02, Greg Kroah-Hartman wrote: >> >>> On Thu, Jul 04, 2019 at 12:13:40PM +0530, Sai Prakash Ranjan wrote: >>> >>>> On 7/4/2019 1:32 AM, Mathieu Poirier wrote: >>>> >>>>> Hi Greg, >>>>> >>>>> On Thu, 27 Jun 2019 at 12:15, Sai Prakash Ranjan wrote: >>>>>> >>>>>> Do not assume the affinity to CPU0 if cpu phandle is omitted. >>>>>> Update the DT binding rules to reflect the same by changing it >>>>>> to a required property. >>>>>> >>>>>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >>>>>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> >>>>> >>>>> I'm all good with this patch - can you pick this up for the coming >>>>> merge window? If not I'll simply keep it in my tree for 5.4. >>>>> >>>>> Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> >>>>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> >>>> >>>> I think you missed adding Greg, adding him now ;) >>> >>> I don't see any patch here for me to actually take :( >> >> I see what you're doing here ^_^ >> >> https://lore.kernel.org/patchwork/patch/1094935/ > > What can I do with a random url? > > Please send patches as emails, if you want me to be able to actually > take it. > > greg k-h > No worries I will resend them. And thanks Marc :)
On 04/07/2019 10:18, Greg Kroah-Hartman wrote: > Marc Gonzalez wrote: > >> https://lore.kernel.org/patchwork/patch/1094935/ > > What can I do with a random url? I dunno, click it? ^_^ More seriously, patchwork provides individual patches, as well as patch series, in the same mbox format used by MUAs, e.g. https://lore.kernel.org/patchwork/patch/1094935/mbox/ https://lore.kernel.org/patchwork/series/400118/mbox/ Then 'git am' works exactly as expected. I suspect you know all this, and it's too big a hassle vs your usual work flow, considering the volume of patches you handle. Just wanted to point it out to those who might not know. Regards.
On Thu, Jul 04, 2019 at 10:51:20AM +0200, Marc Gonzalez wrote: > On 04/07/2019 10:18, Greg Kroah-Hartman wrote: > > > Marc Gonzalez wrote: > > > >> https://lore.kernel.org/patchwork/patch/1094935/ > > > > What can I do with a random url? > > I dunno, click it? ^_^ > > More seriously, patchwork provides individual patches, as well as > patch series, in the same mbox format used by MUAs, e.g. > > https://lore.kernel.org/patchwork/patch/1094935/mbox/ > https://lore.kernel.org/patchwork/series/400118/mbox/ > > Then 'git am' works exactly as expected. > > I suspect you know all this, and it's too big a hassle vs your usual > work flow, considering the volume of patches you handle. And considering that at some times, while traveling, I can _only_ get email, not web access, so I can't rely on patchwork. thanks, greg k-h
diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt index 298291211ea4..f1de3247c1b7 100644 --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -26,8 +26,8 @@ Required properties: processor core is clocked by the internal CPU clock, so it is enabled with CPU clock by default. -- cpu : the CPU phandle the debug module is affined to. When omitted - the module is considered to belong to CPU0. +- cpu : the CPU phandle the debug module is affined to. Do not assume it + to default to CPU0 if omitted. Optional properties: diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 8a88ddebc1a2..fcc3bacfd8bc 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -59,6 +59,11 @@ its hardware characteristcs. * port or ports: see "Graph bindings for Coresight" below. +* Additional required property for Embedded Trace Macrocell (version 3.x and + version 4.x): + * cpu: the cpu phandle this ETM/PTM is affined to. Do not + assume it to default to CPU0 if omitted. + * Additional required properties for System Trace Macrocells (STM): * reg: along with the physical base address and length of the register set as described above, another entry is required to describe the @@ -87,9 +92,6 @@ its hardware characteristcs. * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the - source is considered to belong to CPU0. - * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR