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Fri, 9 Jun 2023 19:56:22 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6455.030; Fri, 9 Jun 2023 19:56:22 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v3 03/25] powerpc/iommu: Setup a default domain and remove set_platform_dma_ops Date: Fri, 9 Jun 2023 16:55:51 -0300 Message-Id: <3-v3-89830a6c7841+43d-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v3-89830a6c7841+43d-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: BY3PR05CA0037.namprd05.prod.outlook.com (2603:10b6:a03:39b::12) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DM4PR12MB5264:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d642ef5-1a52-49e4-e529-08db692397eb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UQDLPQ5GLbyN15x8e9YSsqYLMK4IsURS4f4x7TJpuRM/xosMwurF2o2SwYwz+299SPiTmp51/m6qCy3FPA5GgphUTzz+l4Pr0OzEBc84jgbHescoLtNuV8PRMpvlC0IOJDkWbNdxiwcmCHGt7iIl2UbathwIaWFzXnhqt+xWn9/O2Ei6EAyAI8F9xnKOACq64nkgCqNwTIz35IkwxcrTOr44vX7dd0kwsnJFPBmVtDYXw+ZyPJL63zcaowNiVTv6DGqo3XyQQ1U7u7vSd7vxSZU1i/S2SzOjY+PYlfu6Rw57i8qQJiX8SnTFun7W57vLCx4/q7pZipxEkoPo6XCMiczXHu0oJu4cN3S9URmlI8WI2C0PKphbW0+afrfWBF0pyMWGPyTR0pafeBEY2ELtnhQLECYdksbWpiX/SYf3OQfItMz5Lmld03gRCUKd4Uefsbz9A42pjthEH7Aba9738G5W7zAszZPJfZX/dTgY35alul4T5NivHfJxJ5i5CzFsUfOXM2/TVuPb48z0eiGjo+IlS4nwzspl5aCeCBhCkTh+z7Li7ATXn9VvLpfXGV3VqLaXTALqVV5C3llVdTYR0dB1gsFDCHXlsPhjDOuOcGdwGLxfph1nAhtNiLm00ps47/2Ogul+bmtYfBDyDp/aPObRmftJZWVkCh2DSalrD3+yhTHJYWI4A6UhN+LqwMTfxVx0Ay56c/hMFom1HmevVj+rhGvdrEtXKNSAtdlUqj5xUryEjzzB4obUu+Ooq5NTS6o3oQXrbt2GyT4+plUzSpCWFBjilvkWC58hl970992+qs4qhBYpL70Rq5YnF1pY4abIeDvrFHzEFWKgNQvvGs/+5kR8ERoh3GcMBDIRzcny7PWBt/gQ0Jf097GvDPhqyKpWZ1C5jw4AaY5RDVVAyCxGEbM6xFiIJFFam4Vye4mXVQNt2lr6RH4HSOhJaTzCrc6JoeyjnhvtAWYoypYuB9eX6hgy9X2RUXBBbhnCfq90w+KZxA7Q75QxWFrymGxyi9u9PwmOfwmSu004bejRq28/ETIYrkPziOXAhnVvolC/KSGel83wSQu1krRBryW+c4nyo6BFSbT7qLipi+zFF1xlwpa4JZS3J0NwWGxIibhpzaj/HTHG00OoJ4OK/bEzEAHfvsVb2FdZ0vcW+LifsxPRJdQb9ycyIoKYSiZLOa18RzzJltstg2Xqfc/N+THQAzsJB0nqOsU+/uXBVOPGVovEoilIPIjt7kfuEIuwNnhI+4CbaW73DPOwFH5IMoaAKY9kWSV28QN0lLsphpImpdMPYlto9PE/4mmud5dNUrbuZ8+d7NGA48VUJjFSgCP+Sz3AnfRPk3kcIyeo07lfEeOhIvXeNO7w5OSQqoTkTq3kQKWADkwGbK8+NQl4j5YHKIf8OyQB755Y+7txXb2X4kaWgcjZFdIw46F+NJqLzoh/C7/XsGrDk4A7iP1XaPkEm0oVuasGHty07aKzlsXl6GejxJZ5lexhdhzd40FoS+IEu1bV2bkCe6SJTa4FSBYWzdxKrqrg5+XzkLFOAbXWz32tZT9OdFkj+8B6wfGWUrOe9ACFlxygycZYXs4krS/j X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d642ef5-1a52-49e4-e529-08db692397eb X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2023 19:56:19.8574 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: u530dqdTyF9Vx21F9xSFVxtWsfL3EXm+j3/AhNMcWL92R+lEIfoPUtEgWOlQDgVx X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5264 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org POWER is using the set_platform_dma_ops() callback to hook up its private dma_ops, but this is buired under some indirection and is weirdly happening for a BLOCKED domain as well. For better documentation create a PLATFORM domain to manage the dma_ops, since that is what it is for, and make the BLOCKED domain an alias for it. BLOCKED is required for VFIO. Also removes the leaky allocation of the BLOCKED domain by using a global static. Signed-off-by: Jason Gunthorpe --- arch/powerpc/kernel/iommu.c | 38 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c index 67f0b01e6ff575..0f17cd767e1676 100644 --- a/arch/powerpc/kernel/iommu.c +++ b/arch/powerpc/kernel/iommu.c @@ -1266,7 +1266,7 @@ struct iommu_table_group_ops spapr_tce_table_group_ops = { /* * A simple iommu_ops to allow less cruft in generic VFIO code. */ -static int spapr_tce_blocking_iommu_attach_dev(struct iommu_domain *dom, +static int spapr_tce_platform_iommu_attach_dev(struct iommu_domain *dom, struct device *dev) { struct iommu_group *grp = iommu_group_get(dev); @@ -1283,17 +1283,22 @@ static int spapr_tce_blocking_iommu_attach_dev(struct iommu_domain *dom, return ret; } -static void spapr_tce_blocking_iommu_set_platform_dma(struct device *dev) -{ - struct iommu_group *grp = iommu_group_get(dev); - struct iommu_table_group *table_group; +static const struct iommu_domain_ops spapr_tce_platform_domain_ops = { + .attach_dev = spapr_tce_platform_iommu_attach_dev, +}; - table_group = iommu_group_get_iommudata(grp); - table_group->ops->release_ownership(table_group); -} +static struct iommu_domain spapr_tce_platform_domain = { + .type = IOMMU_DOMAIN_PLATFORM, + .ops = &spapr_tce_platform_domain_ops, +}; -static const struct iommu_domain_ops spapr_tce_blocking_domain_ops = { - .attach_dev = spapr_tce_blocking_iommu_attach_dev, +static struct iommu_domain spapr_tce_blocked_domain = { + .type = IOMMU_DOMAIN_BLOCKED, + /* + * FIXME: SPAPR mixes blocked and platform behaviors, the blocked domain + * also sets the dma_api ops + */ + .ops = &spapr_tce_platform_domain_ops, }; static bool spapr_tce_iommu_capable(struct device *dev, enum iommu_cap cap) @@ -1310,18 +1315,9 @@ static bool spapr_tce_iommu_capable(struct device *dev, enum iommu_cap cap) static struct iommu_domain *spapr_tce_iommu_domain_alloc(unsigned int type) { - struct iommu_domain *dom; - if (type != IOMMU_DOMAIN_BLOCKED) return NULL; - - dom = kzalloc(sizeof(*dom), GFP_KERNEL); - if (!dom) - return NULL; - - dom->ops = &spapr_tce_blocking_domain_ops; - - return dom; + return &spapr_tce_blocked_domain; } static struct iommu_device *spapr_tce_iommu_probe_device(struct device *dev) @@ -1357,12 +1353,12 @@ static struct iommu_group *spapr_tce_iommu_device_group(struct device *dev) } static const struct iommu_ops spapr_tce_iommu_ops = { + .default_domain = &spapr_tce_platform_domain, .capable = spapr_tce_iommu_capable, .domain_alloc = spapr_tce_iommu_domain_alloc, .probe_device = spapr_tce_iommu_probe_device, .release_device = spapr_tce_iommu_release_device, .device_group = spapr_tce_iommu_device_group, - .set_platform_dma_ops = spapr_tce_blocking_iommu_set_platform_dma, }; static struct attribute *spapr_tce_iommu_attrs[] = {