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[v4,1/3] pwm: driver for qualcomm ipq6018 pwm block

Message ID 305eacc9c57c2404795b6be76a08915808e23108.1624771446.git.baruch@tkos.co.il (mailing list archive)
State Not Applicable, archived
Headers show
Series [v4,1/3] pwm: driver for qualcomm ipq6018 pwm block | expand

Commit Message

Baruch Siach June 27, 2021, 5:24 a.m. UTC
Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on
driver from downstream Codeaurora kernel tree. Removed support for older
(V1) variants because I have no access to that hardware.

Tested on IPQ6010 based hardware.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v4:

  Use div64_u64() to fix link for 32-bit targets ((kernel test robot
  <lkp@intel.com>, Uwe Kleine-König)

v3:

  s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)

  Fix integer overflow on 32-bit targets (kernel test robot <lkp@intel.com>)

v2:

Address Uwe Kleine-König review comments:

  Fix period calculation when out of range

  Don't set period larger than requested

  Remove PWM disable on configuration change

  Implement .apply instead of non-atomic .config/.enable/.disable

  Don't modify PWM on .request/.free

  Check pwm_div underflow

  Fix various code and comment formatting issues

Other changes:

  Use u64 divisor safe division

  Remove now empty .request/.free
---
 drivers/pwm/Kconfig   |  12 +++
 drivers/pwm/Makefile  |   1 +
 drivers/pwm/pwm-ipq.c | 238 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 251 insertions(+)
 create mode 100644 drivers/pwm/pwm-ipq.c

Comments

Uwe Kleine-König July 5, 2021, 7:20 a.m. UTC | #1
Hello Baruch,

On Sun, Jun 27, 2021 at 08:24:04AM +0300, Baruch Siach wrote:
> Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on
> driver from downstream Codeaurora kernel tree. Removed support for older
> (V1) variants because I have no access to that hardware.
> 
> Tested on IPQ6010 based hardware.
> 
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> v4:
> 
>   Use div64_u64() to fix link for 32-bit targets ((kernel test robot
>   <lkp@intel.com>, Uwe Kleine-König)
> 
> v3:
> 
>   s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)
> 
>   Fix integer overflow on 32-bit targets (kernel test robot <lkp@intel.com>)
> 
> v2:
> 
> Address Uwe Kleine-König review comments:
> 
>   Fix period calculation when out of range
> 
>   Don't set period larger than requested
> 
>   Remove PWM disable on configuration change
> 
>   Implement .apply instead of non-atomic .config/.enable/.disable
> 
>   Don't modify PWM on .request/.free
> 
>   Check pwm_div underflow
> 
>   Fix various code and comment formatting issues
> 
> Other changes:
> 
>   Use u64 divisor safe division
> 
>   Remove now empty .request/.free
> ---
>  drivers/pwm/Kconfig   |  12 +++
>  drivers/pwm/Makefile  |   1 +
>  drivers/pwm/pwm-ipq.c | 238 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 251 insertions(+)
>  create mode 100644 drivers/pwm/pwm-ipq.c
> 
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index c76adedd58c9..08add845596f 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -260,6 +260,18 @@ config PWM_INTEL_LGM
>  	  To compile this driver as a module, choose M here: the module
>  	  will be called pwm-intel-lgm.
>  
> +config PWM_IPQ
> +	tristate "IPQ PWM support"
> +	depends on ARCH_QCOM || COMPILE_TEST
> +	depends on HAVE_CLK && HAS_IOMEM
> +	help
> +	  Generic PWM framework driver for IPQ PWM block which supports
> +	  4 pwm channels. Each of the these channels can be configured
> +	  independent of each other.
> +
> +	  To compile this driver as a module, choose M here: the module
> +	  will be called pwm-ipq.
> +
>  config PWM_IQS620A
>  	tristate "Azoteq IQS620A PWM support"
>  	depends on MFD_IQS62X || COMPILE_TEST
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index 708840b7fba8..7402feae4b36 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_IMX1)		+= pwm-imx1.o
>  obj-$(CONFIG_PWM_IMX27)		+= pwm-imx27.o
>  obj-$(CONFIG_PWM_IMX_TPM)	+= pwm-imx-tpm.o
>  obj-$(CONFIG_PWM_INTEL_LGM)	+= pwm-intel-lgm.o
> +obj-$(CONFIG_PWM_IPQ)		+= pwm-ipq.o
>  obj-$(CONFIG_PWM_IQS620A)	+= pwm-iqs620a.o
>  obj-$(CONFIG_PWM_JZ4740)	+= pwm-jz4740.o
>  obj-$(CONFIG_PWM_KEEMBAY)	+= pwm-keembay.o
> diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c
> new file mode 100644
> index 000000000000..966b051573c8
> --- /dev/null
> +++ b/drivers/pwm/pwm-ipq.c
> @@ -0,0 +1,238 @@
> +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
> +/*
> + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/math64.h>
> +#include <linux/of_device.h>
> +
> +#define CLK_SRC_FREQ		(100*1000*1000)
> +#define MAX_PWM_DEVICES		4

MAX_PWM_DEVICES is only used once, in my book this doesn't need a define
then. (But if you still want to keep it, that's fine for me, too.)

> +/*
> + * Enable bit is set to enable output toggling in pwm device.
> + * Update bit is set to reflect the changed divider and high duration
> + * values in register.
> + */
> +#define PWM_ENABLE		0x80000000
> +#define PWM_UPDATE		0x40000000
> +
> +/* The frequency range supported is 1Hz to 100MHz */
> +#define MIN_PERIOD_NS	10
> +#define MAX_PERIOD_NS	1000000000

Please use a driver prefix for these defines.

> +
> +/*
> + * The max value specified for each field is based on the number of bits
> + * in the pwm control register for that field
> + */
> +#define MAX_PWM_CFG		0xFFFF
> +
> +#define PWM_CTRL_HI_SHIFT	16
> +
> +#define PWM_CFG_REG0 0 /*PWM_DIV PWM_HI*/
> +#define PWM_CFG_REG1 1 /*ENABLE UPDATE PWM_PRE_DIV*/
> +
> +struct ipq_pwm_chip {
> +	struct pwm_chip chip;
> +	struct clk *clk;
> +	void __iomem *mem;
> +};
> +
> +static struct ipq_pwm_chip *to_ipq_pwm_chip(struct pwm_chip *chip)
> +{
> +	return container_of(chip, struct ipq_pwm_chip, chip);
> +}
> +
> +static unsigned ipq_pwm_reg_offset(struct pwm_device *pwm, unsigned reg)
> +{
> +	return ((pwm->hwpwm * 2) + reg) * 4;
> +}
> +
> +static void config_div_and_duty(struct pwm_device *pwm, int pre_div,
> +			unsigned long long pwm_div, unsigned long period_ns,
> +			unsigned long long duty_ns)

Please also use a consistent prefix for function names.

I suggest to use u64 for some of the parameters. While this doesn't
change anything, it is cleaner as the caller passes variables of this
type.

> +{
> +	unsigned long hi_dur;
> +	unsigned long long quotient;
> +	unsigned long val = 0;
> +	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
> +
> +	/*
> +	 * high duration = pwm duty * (pwm div + 1)
> +	 * pwm duty = duty_ns / period_ns
> +	 */
> +	quotient = (pwm_div + 1) * duty_ns;
> +	hi_dur = div64_u64(quotient, period_ns);
> +
> +	val |= ((hi_dur & MAX_PWM_CFG) << PWM_CTRL_HI_SHIFT);
> +	val |= (pwm_div & MAX_PWM_CFG);
> +	writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG0));

I consider it a bit irritating that the mask is called ...CFG but the
shift define is called ..._CTRL_....

I suggest something like:

	#define IPQ_PWM_REG0	...
	#define IPQ_PWM_REG0_HI		0xffff0000
	#define IPQ_PWM_REG0_DIV	0x0000ffff

	...

	val = FIELD_PREP(IPQ_PWM_REG0_HI, hi_dur) |
		FIELD_PREP(IPQ_PWM_REG0_DIV, pwm_div);

	ipq_pwm_writel(ipq_chip, val, PWM_CFG_REG0);

> +	val = pre_div & MAX_PWM_CFG;
> +	writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG1));
> +}
> +
> +static int ipq_pwm_enable(struct pwm_device *pwm)

This is only called once. The caller (ipq_pwm_apply()) just before
called config_div_and_duty() which already wrote PWM_CFG_REG1. If you
unroll these calls you might fix a glitch or make it more unlikely.

> +{
> +	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
> +	unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1);
> +	unsigned long val;
> +
> +	val = readl(ipq_chip->mem + offset);
> +	val |= PWM_ENABLE | PWM_UPDATE;
> +	writel(val, ipq_chip->mem + offset);
> +
> +	return 0;
> +}
> +
> +static void ipq_pwm_disable(struct pwm_device *pwm)
> +{
> +	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
> +	unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1);
> +	unsigned long val;
> +
> +	val = readl(ipq_chip->mem + offset);
> +	val |= PWM_UPDATE;
> +	val &= ~PWM_ENABLE;
> +	writel(val, ipq_chip->mem + offset);
> +}
> +
> +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> +			 const struct pwm_state *state)
> +{
> +	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(chip);
> +	unsigned long freq;
> +	int pre_div, close_pre_div, close_pwm_div;
> +	int pwm_div;
> +	long long diff;
> +	unsigned long rate = clk_get_rate(ipq_chip->clk);
> +	unsigned long min_diff = rate;
> +	uint64_t fin_ps;
> +	u64 period_ns, duty_ns;
> +
> +	if (state->period < MIN_PERIOD_NS)
> +		return -ERANGE;

MIN_PERIOD_NS depends on clk_get_rate(ipq_chip->clk), doesn't it?

> +	period_ns = min_t(u64, state->period, MAX_PERIOD_NS);
> +	duty_ns = min_t(u64, state->duty_cycle, period_ns);

If you define MAX_PERIOD_NS as (u64)1000000000 you can just use min().

> +
> +	/* freq in Hz for period in nano second*/

Space before the closing */ please

> +	freq = div64_u64(NSEC_PER_SEC, period_ns);
> +	fin_ps = div64_u64(NSEC_PER_SEC * 1000ULL, rate);
> +	close_pre_div = MAX_PWM_CFG;
> +	close_pwm_div = MAX_PWM_CFG;
> +
> +	for (pre_div = 0; pre_div <= MAX_PWM_CFG; pre_div++) {
> +		pwm_div = DIV64_U64_ROUND_CLOSEST(period_ns * 1000,
> +						  fin_ps * (pre_div + 1));
> +		pwm_div--;
> +		if (pwm_div < 0 || pwm_div > MAX_PWM_CFG)
> +			continue;
> +
> +		diff = ((uint64_t)freq * (pre_div + 1) * (pwm_div + 1))
> +			- (uint64_t)rate;
> +
> +		if (diff < 0) /* period larger than requested */
> +			continue;
> +		if (diff == 0) { /* bingo */
> +			close_pre_div = pre_div;
> +			close_pwm_div = pwm_div;
> +			break;
> +		}
> +		if (diff < min_diff) {
> +			min_diff = diff;
> +			close_pre_div = pre_div;
> +			close_pwm_div = pwm_div;
> +		}

I didn't check deeply, but I assume this calculation can be done more
efficiently. Also I wonder if DIV64_U64_ROUND_CLOSEST is right. When you
implement a .get_state() callback (which usually helps me to understand
how the hardware works) I'm willing to take a closer look.

> +	}
> +
> +	/* config divider values for the closest possible frequency */
> +	config_div_and_duty(pwm, close_pre_div, close_pwm_div,
> +			    period_ns, duty_ns);
> +	if (state->enabled)
> +		ipq_pwm_enable(pwm);
> +	else
> +		ipq_pwm_disable(pwm);
> +
> +	return 0;
> +}
> +
> +static struct pwm_ops ipq_pwm_ops = {
> +	.apply = ipq_pwm_apply,

Please implement a .get_state() function. (And in general, test your patch
with PWM_DEBUG enabled.)

> +	.owner = THIS_MODULE,
> +};
> +
> +static int ipq_pwm_probe(struct platform_device *pdev)
> +{
> +	struct ipq_pwm_chip *pwm;
> +	struct device *dev;
> +	int ret;
> +
> +	dev = &pdev->dev;

This can go to the line declaring dev.

> +	pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
> +	if (!pwm)
> +		return -ENOMEM;
> +
> +	platform_set_drvdata(pdev, pwm);
> +
> +	pwm->mem = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(pwm->mem))
> +		return PTR_ERR(pwm->mem);
> +
> +	pwm->clk = devm_clk_get(dev, "core");
> +	if (IS_ERR(pwm->clk))

Error message please. Preferably using dev_err_probe().

> +		return PTR_ERR(pwm->clk);
> +
> +	ret = clk_set_rate(pwm->clk, CLK_SRC_FREQ);
> +	if (ret)

ditto.

> +		return ret;

empty line here?

> +	ret = clk_prepare_enable(pwm->clk);
> +	if (ret)

ditto.

> +		return ret;
> +
> +	pwm->chip.dev = dev;
> +	pwm->chip.ops = &ipq_pwm_ops;
> +	pwm->chip.npwm = MAX_PWM_DEVICES;
> +
> +	ret = pwmchip_add(&pwm->chip);
> +	if (ret < 0) {
> +		dev_err_probe(dev, ret, "pwmchip_add() failed\n");
> +		clk_disable_unprepare(pwm->clk);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int ipq_pwm_remove(struct platform_device *pdev)
> +{
> +	struct ipq_pwm_chip *pwm = platform_get_drvdata(pdev);
> +
> +	pwmchip_remove(&pwm->chip);

clk_disable_unprepare missing here.

> +
> +	return 0;
> +}
> +
> +static const struct of_device_id pwm_ipq_dt_match[] = {
> +	{ .compatible = "qcom,ipq6018-pwm", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match);
> +
> +static struct platform_driver ipq_pwm_driver = {
> +	.driver = {
> +		.name = "ipq-pwm",
> +		.owner = THIS_MODULE,

Setting owner isn't necessary any more since v3.11 (commit 9447057eaff8
("platform_device: use a macro instead of platform_driver_register").

> +		.of_match_table = pwm_ipq_dt_match,
> +	},
> +	.probe = ipq_pwm_probe,
> +	.remove = ipq_pwm_remove,
> +};
> +
> +module_platform_driver(ipq_pwm_driver);
> +
> +MODULE_LICENSE("Dual BSD/GPL");
> -- 
> 2.30.2
> 
>
Baruch Siach July 7, 2021, 4:58 a.m. UTC | #2
Hi Uwe,

Thanks for taking the time to review this patch. I have a few comment
below.

On Mon, Jul 05 2021, Uwe Kleine-König wrote:
> On Sun, Jun 27, 2021 at 08:24:04AM +0300, Baruch Siach wrote:
>> +/*
>> + * Enable bit is set to enable output toggling in pwm device.
>> + * Update bit is set to reflect the changed divider and high duration
>> + * values in register.
>> + */
>> +#define PWM_ENABLE		0x80000000
>> +#define PWM_UPDATE		0x40000000
>> +
>> +/* The frequency range supported is 1Hz to 100MHz */
>> +#define MIN_PERIOD_NS	10
>> +#define MAX_PERIOD_NS	1000000000
>
> Please use a driver prefix for these defines.

I take this to refer also to the defines below, right?

>> +
>> +/*
>> + * The max value specified for each field is based on the number of bits
>> + * in the pwm control register for that field
>> + */
>> +#define MAX_PWM_CFG		0xFFFF
>> +
>> +#define PWM_CTRL_HI_SHIFT	16
>> +
>> +#define PWM_CFG_REG0 0 /*PWM_DIV PWM_HI*/
>> +#define PWM_CFG_REG1 1 /*ENABLE UPDATE PWM_PRE_DIV*/

...

>> +static void config_div_and_duty(struct pwm_device *pwm, int pre_div,
>> +			unsigned long long pwm_div, unsigned long period_ns,
>> +			unsigned long long duty_ns)
>
> Please also use a consistent prefix for function names.
>
> I suggest to use u64 for some of the parameters. While this doesn't
> change anything, it is cleaner as the caller passes variables of this
> type.

Actually for pre_div and pwm_div the caller passes int values. I agree
this is inconsistent.

...

>> +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>> +			 const struct pwm_state *state)
>> +{
>> +	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(chip);
>> +	unsigned long freq;
>> +	int pre_div, close_pre_div, close_pwm_div;
>> +	int pwm_div;
>> +	long long diff;
>> +	unsigned long rate = clk_get_rate(ipq_chip->clk);
>> +	unsigned long min_diff = rate;
>> +	uint64_t fin_ps;
>> +	u64 period_ns, duty_ns;
>> +
>> +	if (state->period < MIN_PERIOD_NS)
>> +		return -ERANGE;
>
> MIN_PERIOD_NS depends on clk_get_rate(ipq_chip->clk), doesn't it?

probe sets this clock to the fixed 100MHz rate (CLK_SRC_FREQ). Would you
prefer to derive MIN_PERIOD_NS from CLK_SRC_FREQ?

>> +	period_ns = min_t(u64, state->period, MAX_PERIOD_NS);
>> +	duty_ns = min_t(u64, state->duty_cycle, period_ns);
>
> If you define MAX_PERIOD_NS as (u64)1000000000 you can just use min().
>
>> +
>> +	/* freq in Hz for period in nano second*/
>
> Space before the closing */ please
>
>> +	freq = div64_u64(NSEC_PER_SEC, period_ns);
>> +	fin_ps = div64_u64(NSEC_PER_SEC * 1000ULL, rate);
>> +	close_pre_div = MAX_PWM_CFG;
>> +	close_pwm_div = MAX_PWM_CFG;
>> +
>> +	for (pre_div = 0; pre_div <= MAX_PWM_CFG; pre_div++) {
>> +		pwm_div = DIV64_U64_ROUND_CLOSEST(period_ns * 1000,
>> +						  fin_ps * (pre_div + 1));
>> +		pwm_div--;
>> +		if (pwm_div < 0 || pwm_div > MAX_PWM_CFG)
>> +			continue;
>> +
>> +		diff = ((uint64_t)freq * (pre_div + 1) * (pwm_div + 1))
>> +			- (uint64_t)rate;
>> +
>> +		if (diff < 0) /* period larger than requested */
>> +			continue;
>> +		if (diff == 0) { /* bingo */
>> +			close_pre_div = pre_div;
>> +			close_pwm_div = pwm_div;
>> +			break;
>> +		}
>> +		if (diff < min_diff) {
>> +			min_diff = diff;
>> +			close_pre_div = pre_div;
>> +			close_pwm_div = pwm_div;
>> +		}
>
> I didn't check deeply, but I assume this calculation can be done more
> efficiently.

The thing is that we have two dividers to play with. I can't think of a
cleaner way to find the best match for a given target frequency.

> Also I wonder if DIV64_U64_ROUND_CLOSEST is right. When you implement
> a .get_state() callback (which usually helps me to understand how the
> hardware works) I'm willing to take a closer look.

Thanks,
baruch
Uwe Kleine-König July 7, 2021, 5:42 a.m. UTC | #3
Hello Baruch,

On Wed, Jul 07, 2021 at 07:58:01AM +0300, Baruch Siach wrote:
> On Mon, Jul 05 2021, Uwe Kleine-König wrote:
> > On Sun, Jun 27, 2021 at 08:24:04AM +0300, Baruch Siach wrote:
> >> +/*
> >> + * Enable bit is set to enable output toggling in pwm device.
> >> + * Update bit is set to reflect the changed divider and high duration
> >> + * values in register.
> >> + */
> >> +#define PWM_ENABLE		0x80000000
> >> +#define PWM_UPDATE		0x40000000
> >> +
> >> +/* The frequency range supported is 1Hz to 100MHz */
> >> +#define MIN_PERIOD_NS	10
> >> +#define MAX_PERIOD_NS	1000000000
> >
> > Please use a driver prefix for these defines.
> 
> I take this to refer also to the defines below, right?

right.

> >> +
> >> +/*
> >> + * The max value specified for each field is based on the number of bits
> >> + * in the pwm control register for that field
> >> + */
> >> +#define MAX_PWM_CFG		0xFFFF
> >> +
> >> +#define PWM_CTRL_HI_SHIFT	16
> >> +
> >> +#define PWM_CFG_REG0 0 /*PWM_DIV PWM_HI*/
> >> +#define PWM_CFG_REG1 1 /*ENABLE UPDATE PWM_PRE_DIV*/
> 
> ...
> 
> >> +static void config_div_and_duty(struct pwm_device *pwm, int pre_div,
> >> +			unsigned long long pwm_div, unsigned long period_ns,
> >> +			unsigned long long duty_ns)
> >
> > Please also use a consistent prefix for function names.
> >
> > I suggest to use u64 for some of the parameters. While this doesn't
> > change anything, it is cleaner as the caller passes variables of this
> > type.
> 
> Actually for pre_div and pwm_div the caller passes int values. I agree
> this is inconsistent.
> 
> ...
> 
> >> +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> >> +			 const struct pwm_state *state)
> >> +{
> >> +	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(chip);
> >> +	unsigned long freq;
> >> +	int pre_div, close_pre_div, close_pwm_div;
> >> +	int pwm_div;
> >> +	long long diff;
> >> +	unsigned long rate = clk_get_rate(ipq_chip->clk);
> >> +	unsigned long min_diff = rate;
> >> +	uint64_t fin_ps;
> >> +	u64 period_ns, duty_ns;
> >> +
> >> +	if (state->period < MIN_PERIOD_NS)
> >> +		return -ERANGE;
> >
> > MIN_PERIOD_NS depends on clk_get_rate(ipq_chip->clk), doesn't it?
> 
> probe sets this clock to the fixed 100MHz rate (CLK_SRC_FREQ). Would you
> prefer to derive MIN_PERIOD_NS from CLK_SRC_FREQ?

I'd like to either have all of ipq_pwm_apply use this information that
the clock rate is 100MHz or nothing, but having MIN_PERIOD_NS hardcoding
that information and use clk_get_rate(ipq_chip->clk) for calculating
fin_ps is strange.

> >> +	freq = div64_u64(NSEC_PER_SEC, period_ns);
> >> +	fin_ps = div64_u64(NSEC_PER_SEC * 1000ULL, rate);
> >> +	close_pre_div = MAX_PWM_CFG;
> >> +	close_pwm_div = MAX_PWM_CFG;
> >> +
> >> +	for (pre_div = 0; pre_div <= MAX_PWM_CFG; pre_div++) {
> >> +		pwm_div = DIV64_U64_ROUND_CLOSEST(period_ns * 1000,
> >> +						  fin_ps * (pre_div + 1));
> >> +		pwm_div--;
> >> +		if (pwm_div < 0 || pwm_div > MAX_PWM_CFG)
> >> +			continue;
> >> +
> >> +		diff = ((uint64_t)freq * (pre_div + 1) * (pwm_div + 1))
> >> +			- (uint64_t)rate;
> >> +
> >> +		if (diff < 0) /* period larger than requested */
> >> +			continue;
> >> +		if (diff == 0) { /* bingo */
> >> +			close_pre_div = pre_div;
> >> +			close_pwm_div = pwm_div;
> >> +			break;
> >> +		}
> >> +		if (diff < min_diff) {
> >> +			min_diff = diff;
> >> +			close_pre_div = pre_div;
> >> +			close_pwm_div = pwm_div;
> >> +		}
> >
> > I didn't check deeply, but I assume this calculation can be done more
> > efficiently.
> 
> The thing is that we have two dividers to play with. I can't think of a
> cleaner way to find the best match for a given target frequency.

OK, with two equal dividers it might indeed be necessary to do it this
way. After seeing a get_state implemententation I will think about this
some more.

Best regards
Uwe
diff mbox series

Patch

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index c76adedd58c9..08add845596f 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -260,6 +260,18 @@  config PWM_INTEL_LGM
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-intel-lgm.
 
+config PWM_IPQ
+	tristate "IPQ PWM support"
+	depends on ARCH_QCOM || COMPILE_TEST
+	depends on HAVE_CLK && HAS_IOMEM
+	help
+	  Generic PWM framework driver for IPQ PWM block which supports
+	  4 pwm channels. Each of the these channels can be configured
+	  independent of each other.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-ipq.
+
 config PWM_IQS620A
 	tristate "Azoteq IQS620A PWM support"
 	depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 708840b7fba8..7402feae4b36 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -22,6 +22,7 @@  obj-$(CONFIG_PWM_IMX1)		+= pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)		+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)	+= pwm-imx-tpm.o
 obj-$(CONFIG_PWM_INTEL_LGM)	+= pwm-intel-lgm.o
+obj-$(CONFIG_PWM_IPQ)		+= pwm-ipq.o
 obj-$(CONFIG_PWM_IQS620A)	+= pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)	+= pwm-jz4740.o
 obj-$(CONFIG_PWM_KEEMBAY)	+= pwm-keembay.o
diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c
new file mode 100644
index 000000000000..966b051573c8
--- /dev/null
+++ b/drivers/pwm/pwm-ipq.c
@@ -0,0 +1,238 @@ 
+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
+/*
+ * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/math64.h>
+#include <linux/of_device.h>
+
+#define CLK_SRC_FREQ		(100*1000*1000)
+#define MAX_PWM_DEVICES		4
+
+/*
+ * Enable bit is set to enable output toggling in pwm device.
+ * Update bit is set to reflect the changed divider and high duration
+ * values in register.
+ */
+#define PWM_ENABLE		0x80000000
+#define PWM_UPDATE		0x40000000
+
+/* The frequency range supported is 1Hz to 100MHz */
+#define MIN_PERIOD_NS	10
+#define MAX_PERIOD_NS	1000000000
+
+/*
+ * The max value specified for each field is based on the number of bits
+ * in the pwm control register for that field
+ */
+#define MAX_PWM_CFG		0xFFFF
+
+#define PWM_CTRL_HI_SHIFT	16
+
+#define PWM_CFG_REG0 0 /*PWM_DIV PWM_HI*/
+#define PWM_CFG_REG1 1 /*ENABLE UPDATE PWM_PRE_DIV*/
+
+struct ipq_pwm_chip {
+	struct pwm_chip chip;
+	struct clk *clk;
+	void __iomem *mem;
+};
+
+static struct ipq_pwm_chip *to_ipq_pwm_chip(struct pwm_chip *chip)
+{
+	return container_of(chip, struct ipq_pwm_chip, chip);
+}
+
+static unsigned ipq_pwm_reg_offset(struct pwm_device *pwm, unsigned reg)
+{
+	return ((pwm->hwpwm * 2) + reg) * 4;
+}
+
+static void config_div_and_duty(struct pwm_device *pwm, int pre_div,
+			unsigned long long pwm_div, unsigned long period_ns,
+			unsigned long long duty_ns)
+{
+	unsigned long hi_dur;
+	unsigned long long quotient;
+	unsigned long val = 0;
+	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
+
+	/*
+	 * high duration = pwm duty * (pwm div + 1)
+	 * pwm duty = duty_ns / period_ns
+	 */
+	quotient = (pwm_div + 1) * duty_ns;
+	hi_dur = div64_u64(quotient, period_ns);
+
+	val |= ((hi_dur & MAX_PWM_CFG) << PWM_CTRL_HI_SHIFT);
+	val |= (pwm_div & MAX_PWM_CFG);
+	writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG0));
+	val = pre_div & MAX_PWM_CFG;
+	writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG1));
+}
+
+static int ipq_pwm_enable(struct pwm_device *pwm)
+{
+	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
+	unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1);
+	unsigned long val;
+
+	val = readl(ipq_chip->mem + offset);
+	val |= PWM_ENABLE | PWM_UPDATE;
+	writel(val, ipq_chip->mem + offset);
+
+	return 0;
+}
+
+static void ipq_pwm_disable(struct pwm_device *pwm)
+{
+	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip);
+	unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1);
+	unsigned long val;
+
+	val = readl(ipq_chip->mem + offset);
+	val |= PWM_UPDATE;
+	val &= ~PWM_ENABLE;
+	writel(val, ipq_chip->mem + offset);
+}
+
+static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+			 const struct pwm_state *state)
+{
+	struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(chip);
+	unsigned long freq;
+	int pre_div, close_pre_div, close_pwm_div;
+	int pwm_div;
+	long long diff;
+	unsigned long rate = clk_get_rate(ipq_chip->clk);
+	unsigned long min_diff = rate;
+	uint64_t fin_ps;
+	u64 period_ns, duty_ns;
+
+	if (state->period < MIN_PERIOD_NS)
+		return -ERANGE;
+
+	period_ns = min_t(u64, state->period, MAX_PERIOD_NS);
+	duty_ns = min_t(u64, state->duty_cycle, period_ns);
+
+	/* freq in Hz for period in nano second*/
+	freq = div64_u64(NSEC_PER_SEC, period_ns);
+	fin_ps = div64_u64(NSEC_PER_SEC * 1000ULL, rate);
+	close_pre_div = MAX_PWM_CFG;
+	close_pwm_div = MAX_PWM_CFG;
+
+	for (pre_div = 0; pre_div <= MAX_PWM_CFG; pre_div++) {
+		pwm_div = DIV64_U64_ROUND_CLOSEST(period_ns * 1000,
+						  fin_ps * (pre_div + 1));
+		pwm_div--;
+		if (pwm_div < 0 || pwm_div > MAX_PWM_CFG)
+			continue;
+
+		diff = ((uint64_t)freq * (pre_div + 1) * (pwm_div + 1))
+			- (uint64_t)rate;
+
+		if (diff < 0) /* period larger than requested */
+			continue;
+		if (diff == 0) { /* bingo */
+			close_pre_div = pre_div;
+			close_pwm_div = pwm_div;
+			break;
+		}
+		if (diff < min_diff) {
+			min_diff = diff;
+			close_pre_div = pre_div;
+			close_pwm_div = pwm_div;
+		}
+	}
+
+	/* config divider values for the closest possible frequency */
+	config_div_and_duty(pwm, close_pre_div, close_pwm_div,
+			    period_ns, duty_ns);
+	if (state->enabled)
+		ipq_pwm_enable(pwm);
+	else
+		ipq_pwm_disable(pwm);
+
+	return 0;
+}
+
+static struct pwm_ops ipq_pwm_ops = {
+	.apply = ipq_pwm_apply,
+	.owner = THIS_MODULE,
+};
+
+static int ipq_pwm_probe(struct platform_device *pdev)
+{
+	struct ipq_pwm_chip *pwm;
+	struct device *dev;
+	int ret;
+
+	dev = &pdev->dev;
+	pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
+	if (!pwm)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, pwm);
+
+	pwm->mem = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(pwm->mem))
+		return PTR_ERR(pwm->mem);
+
+	pwm->clk = devm_clk_get(dev, "core");
+	if (IS_ERR(pwm->clk))
+		return PTR_ERR(pwm->clk);
+
+	ret = clk_set_rate(pwm->clk, CLK_SRC_FREQ);
+	if (ret)
+		return ret;
+	ret = clk_prepare_enable(pwm->clk);
+	if (ret)
+		return ret;
+
+	pwm->chip.dev = dev;
+	pwm->chip.ops = &ipq_pwm_ops;
+	pwm->chip.npwm = MAX_PWM_DEVICES;
+
+	ret = pwmchip_add(&pwm->chip);
+	if (ret < 0) {
+		dev_err_probe(dev, ret, "pwmchip_add() failed\n");
+		clk_disable_unprepare(pwm->clk);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ipq_pwm_remove(struct platform_device *pdev)
+{
+	struct ipq_pwm_chip *pwm = platform_get_drvdata(pdev);
+
+	pwmchip_remove(&pwm->chip);
+
+	return 0;
+}
+
+static const struct of_device_id pwm_ipq_dt_match[] = {
+	{ .compatible = "qcom,ipq6018-pwm", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match);
+
+static struct platform_driver ipq_pwm_driver = {
+	.driver = {
+		.name = "ipq-pwm",
+		.owner = THIS_MODULE,
+		.of_match_table = pwm_ipq_dt_match,
+	},
+	.probe = ipq_pwm_probe,
+	.remove = ipq_pwm_remove,
+};
+
+module_platform_driver(ipq_pwm_driver);
+
+MODULE_LICENSE("Dual BSD/GPL");