From patchwork Fri Oct 31 02:33:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ganesan, Aravind" X-Patchwork-Id: 5201631 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 21C069F349 for ; Fri, 31 Oct 2014 02:33:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 283E2201B4 for ; Fri, 31 Oct 2014 02:33:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9047201ED for ; Fri, 31 Oct 2014 02:33:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1422713AbaJaCd2 (ORCPT ); Thu, 30 Oct 2014 22:33:28 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:50620 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1422652AbaJaCd1 (ORCPT ); Thu, 30 Oct 2014 22:33:27 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 745B1140006; Fri, 31 Oct 2014 02:33:27 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 66672140008; Fri, 31 Oct 2014 02:33:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from [10.0.0.8] (c-73-3-154-58.hsd1.co.comcast.net [73.3.154.58]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: aravindg@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id F010E140006; Fri, 31 Oct 2014 02:33:25 +0000 (UTC) Message-ID: <5452F4F5.6000705@codeaurora.org> Date: Thu, 30 Oct 2014 20:33:25 -0600 From: "Ganesan, Aravind" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: freedreno@lists.freedesktop.org, Rob Clark CC: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Jordan Crouse , rishib@quicinc.com Subject: [PATCH] drm/msm: Don't split an IB at the end of ring buffer. X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Splitting the command sequence for an IB1 submission at the end of the ring buffer can hang the GPU. To fix this, if there isn't enough contiguous space at the end to fit the full command sequence, insert NOPs at the end, and write the sequence at the start, as space becomes available. Signed-off-by: Aravind Ganesan --- Resend in patch-set format and with dri-devel@lists.freedesktop.org on the CC. drivers/gpu/drm/msm/adreno/adreno_gpu.c | 45 ++++++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 +++--- 2 files changed, 46 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 1fe7c8d..51901df 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -281,10 +281,49 @@ static uint32_t ring_freewords(struct msm_gpu *gpu) return (rptr + (size - 1) - wptr) % size; } -void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords) +void adreno_wait_ring_contiguous(struct msm_gpu *gpu, + uint32_t ndwords) { - if (spin_until(ring_freewords(gpu) >= ndwords)) - DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name); + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + uint32_t size = gpu->rb->size/4; + uint32_t wptr; + uint32_t rptr; + + /* Wait for free space and then check if they are contiguous */ + if(spin_until(ring_freewords(gpu)>= ndwords)){ + DRM_ERROR("%s: timeout waiting for ringbuffer space\n", + gpu->name); + return; + } + + wptr = get_wptr(gpu->rb); + rptr = adreno_gpu->memptrs->rptr; + + /* We have enough space in the ring for ndwords. Three conditions + * indicates we have contigous space: + * (1) wptr can be equal to size, ring has wrapped and wptr is 0 + * (see OUT_RING), meaning we have enough space. + * (2) We have enough space in the ring, wptr < rptr indicates + * enough contiguous space + * (3) wptr + ndwords < size - 1 implies enough space in the ring. + */ + if((wptr == size) || (wptr < rptr) || (wptr + ndwords < size - 1)) + return; + + /* Fill the end of ring with no-ops + * */ + OUT_RING(gpu->rb, CP_TYPE3_PKT | (((size - wptr - 1) - 1) << 16) | + ((CP_NOP & 0xFF) << 8)); + gpu->rb->cur = gpu->rb->start; + + /* We have reset cur pointer to start. If ring_freewords returns + * greater than ndwords, then we have contigous space. + * */ + if(spin_until(ring_freewords(gpu)>= ndwords)){ + DRM_ERROR("%s: timeout waiting for ringbuffer space\n", + gpu->name); + return; + } } static const char *iommu_ports[] = { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 3fa06b3..47ba8f5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -247,7 +247,7 @@ void adreno_idle(struct msm_gpu *gpu); void adreno_show(struct msm_gpu *gpu, struct seq_file *m); #endif void adreno_dump(struct msm_gpu *gpu); -void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords); +void adreno_wait_ring_contiguous(struct msm_gpu *gpu, uint32_t ndwords); int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs); @@ -259,7 +259,7 @@ void adreno_gpu_cleanup(struct adreno_gpu *gpu); static inline void OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) { - adreno_wait_ring(ring->gpu, cnt+1); + adreno_wait_ring_contiguous(ring->gpu, cnt+1); OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); } @@ -267,14 +267,14 @@ OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) static inline void OUT_PKT2(struct msm_ringbuffer *ring) { - adreno_wait_ring(ring->gpu, 1); + adreno_wait_ring_contiguous(ring->gpu, 1); OUT_RING(ring, CP_TYPE2_PKT); } static inline void OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) { - adreno_wait_ring(ring->gpu, cnt+1); + adreno_wait_ring_contiguous(ring->gpu, cnt+1); OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); }