[1/3] drm/msm: Additional definitions for a3xx and a4xx

Updated a3xx and a4xx headers, generated from rnndb files:
https://github.com/freedreno/envytools


Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org>
---
Resend the patch-set with the same thread-id
Resend in patch-set format and with dri-devel@lists.freedesktop.org on
the CC.
 drivers/gpu/drm/msm/adreno/a3xx.xml.h |   50 +-
 drivers/gpu/drm/msm/adreno/a4xx.xml.h | 2062
+++++++++++++++++++++++++++++++++
 2 files changed, 2102 insertions(+), 10 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/adreno/a4xx.xml.h

A4XX_HLSQ_FS_CONTROL_CONSTLENGTH__MASK;
+}
+#define A4XX_HLSQ_FS_CONTROL_CONSTOBJECTOFFSET__MASK		0x0000ff00
+#define A4XX_HLSQ_FS_CONTROL_CONSTOBJECTOFFSET__SHIFT		8
+static inline uint32_t A4XX_HLSQ_FS_CONTROL_CONSTOBJECTOFFSET(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_FS_CONTROL_CONSTOBJECTOFFSET__SHIFT) &
A4XX_HLSQ_FS_CONTROL_CONSTOBJECTOFFSET__MASK;
+}
+#define A4XX_HLSQ_FS_CONTROL_SHADEROBJOFFSET__MASK		0x00fe0000
+#define A4XX_HLSQ_FS_CONTROL_SHADEROBJOFFSET__SHIFT		17
+static inline uint32_t A4XX_HLSQ_FS_CONTROL_SHADEROBJOFFSET(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_FS_CONTROL_SHADEROBJOFFSET__SHIFT) &
A4XX_HLSQ_FS_CONTROL_SHADEROBJOFFSET__MASK;
+}
+#define A4XX_HLSQ_FS_CONTROL_INSTRLENGTH__MASK			0xff000000
+#define A4XX_HLSQ_FS_CONTROL_INSTRLENGTH__SHIFT			24
+static inline uint32_t A4XX_HLSQ_FS_CONTROL_INSTRLENGTH(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_FS_CONTROL_INSTRLENGTH__SHIFT) &
A4XX_HLSQ_FS_CONTROL_INSTRLENGTH__MASK;
+}
+
+#define REG_A4XX_HLSQ_HS_CONTROL				0x000023c7
+#define A4XX_HLSQ_HS_CONTROL_CONSTLENGTH__MASK			0x000000ff
+#define A4XX_HLSQ_HS_CONTROL_CONSTLENGTH__SHIFT			0
+static inline uint32_t A4XX_HLSQ_HS_CONTROL_CONSTLENGTH(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_HS_CONTROL_CONSTLENGTH__SHIFT) &
A4XX_HLSQ_HS_CONTROL_CONSTLENGTH__MASK;
+}
+#define A4XX_HLSQ_HS_CONTROL_CONSTOBJECTOFFSET__MASK		0x0000ff00
+#define A4XX_HLSQ_HS_CONTROL_CONSTOBJECTOFFSET__SHIFT		8
+static inline uint32_t A4XX_HLSQ_HS_CONTROL_CONSTOBJECTOFFSET(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_HS_CONTROL_CONSTOBJECTOFFSET__SHIFT) &
A4XX_HLSQ_HS_CONTROL_CONSTOBJECTOFFSET__MASK;
+}
+#define A4XX_HLSQ_HS_CONTROL_SHADEROBJOFFSET__MASK		0x00fe0000
+#define A4XX_HLSQ_HS_CONTROL_SHADEROBJOFFSET__SHIFT		17
+static inline uint32_t A4XX_HLSQ_HS_CONTROL_SHADEROBJOFFSET(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_HS_CONTROL_SHADEROBJOFFSET__SHIFT) &
A4XX_HLSQ_HS_CONTROL_SHADEROBJOFFSET__MASK;
+}
+#define A4XX_HLSQ_HS_CONTROL_INSTRLENGTH__MASK			0xff000000
+#define A4XX_HLSQ_HS_CONTROL_INSTRLENGTH__SHIFT			24
+static inline uint32_t A4XX_HLSQ_HS_CONTROL_INSTRLENGTH(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_HS_CONTROL_INSTRLENGTH__SHIFT) &
A4XX_HLSQ_HS_CONTROL_INSTRLENGTH__MASK;
+}
+
+#define REG_A4XX_HLSQ_DS_CONTROL				0x000023c8
+#define A4XX_HLSQ_DS_CONTROL_CONSTLENGTH__MASK			0x000000ff
+#define A4XX_HLSQ_DS_CONTROL_CONSTLENGTH__SHIFT			0
+static inline uint32_t A4XX_HLSQ_DS_CONTROL_CONSTLENGTH(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_DS_CONTROL_CONSTLENGTH__SHIFT) &
A4XX_HLSQ_DS_CONTROL_CONSTLENGTH__MASK;
+}
+#define A4XX_HLSQ_DS_CONTROL_CONSTOBJECTOFFSET__MASK		0x0000ff00
+#define A4XX_HLSQ_DS_CONTROL_CONSTOBJECTOFFSET__SHIFT		8
+static inline uint32_t A4XX_HLSQ_DS_CONTROL_CONSTOBJECTOFFSET(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_DS_CONTROL_CONSTOBJECTOFFSET__SHIFT) &
A4XX_HLSQ_DS_CONTROL_CONSTOBJECTOFFSET__MASK;
+}
+#define A4XX_HLSQ_DS_CONTROL_SHADEROBJOFFSET__MASK		0x00fe0000
+#define A4XX_HLSQ_DS_CONTROL_SHADEROBJOFFSET__SHIFT		17
+static inline uint32_t A4XX_HLSQ_DS_CONTROL_SHADEROBJOFFSET(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_DS_CONTROL_SHADEROBJOFFSET__SHIFT) &
A4XX_HLSQ_DS_CONTROL_SHADEROBJOFFSET__MASK;
+}
+#define A4XX_HLSQ_DS_CONTROL_INSTRLENGTH__MASK			0xff000000
+#define A4XX_HLSQ_DS_CONTROL_INSTRLENGTH__SHIFT			24
+static inline uint32_t A4XX_HLSQ_DS_CONTROL_INSTRLENGTH(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_DS_CONTROL_INSTRLENGTH__SHIFT) &
A4XX_HLSQ_DS_CONTROL_INSTRLENGTH__MASK;
+}
+
+#define REG_A4XX_HLSQ_GS_CONTROL				0x000023c9
+#define A4XX_HLSQ_GS_CONTROL_CONSTLENGTH__MASK			0x000000ff
+#define A4XX_HLSQ_GS_CONTROL_CONSTLENGTH__SHIFT			0
+static inline uint32_t A4XX_HLSQ_GS_CONTROL_CONSTLENGTH(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_GS_CONTROL_CONSTLENGTH__SHIFT) &
A4XX_HLSQ_GS_CONTROL_CONSTLENGTH__MASK;
+}
+#define A4XX_HLSQ_GS_CONTROL_CONSTOBJECTOFFSET__MASK		0x0000ff00
+#define A4XX_HLSQ_GS_CONTROL_CONSTOBJECTOFFSET__SHIFT		8
+static inline uint32_t A4XX_HLSQ_GS_CONTROL_CONSTOBJECTOFFSET(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_GS_CONTROL_CONSTOBJECTOFFSET__SHIFT) &
A4XX_HLSQ_GS_CONTROL_CONSTOBJECTOFFSET__MASK;
+}
+#define A4XX_HLSQ_GS_CONTROL_SHADEROBJOFFSET__MASK		0x00fe0000
+#define A4XX_HLSQ_GS_CONTROL_SHADEROBJOFFSET__SHIFT		17
+static inline uint32_t A4XX_HLSQ_GS_CONTROL_SHADEROBJOFFSET(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_GS_CONTROL_SHADEROBJOFFSET__SHIFT) &
A4XX_HLSQ_GS_CONTROL_SHADEROBJOFFSET__MASK;
+}
+#define A4XX_HLSQ_GS_CONTROL_INSTRLENGTH__MASK			0xff000000
+#define A4XX_HLSQ_GS_CONTROL_INSTRLENGTH__SHIFT			24
+static inline uint32_t A4XX_HLSQ_GS_CONTROL_INSTRLENGTH(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_GS_CONTROL_INSTRLENGTH__SHIFT) &
A4XX_HLSQ_GS_CONTROL_INSTRLENGTH__MASK;
+}
+
+#define REG_A4XX_HLSQ_UPDATE_CONTROL				0x000023db
+
+#define REG_A4XX_PC_BINNING_COMMAND				0x00000d00
+#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE			0x00000001
+
+#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE			0x00000d0c
+
+#define REG_A4XX_PC_PERFCTR_PC_SEL_0				0x00000d10
+
+#define REG_A4XX_PC_PERFCTR_PC_SEL_7				0x00000d17
+
+#define REG_A4XX_PC_BIN_BASE					0x000021c0
+
+#define REG_A4XX_PC_PRIM_VTX_CNTL				0x000021c4
+#define A4XX_PC_PRIM_VTX_CNTL_VAROUT				0x00000001
+#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST		0x02000000
+#define A4XX_PC_PRIM_VTX_CNTL_PSIZE				0x04000000
+
+#define REG_A4XX_PC_RESTART_INDEX				0x000021c6
+
+#define REG_A4XX_PC_GS_PARAM					0x000021e5
+
+#define REG_A4XX_PC_HS_PARAM					0x000021e7
+
+#define REG_A4XX_VBIF_VERSION					0x00003000
+
+#define REG_A4XX_VBIF_CLKON					0x00003001
+#define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS			0x00000001
+
+#define REG_A4XX_VBIF_ABIT_SORT					0x0000301c
+
+#define REG_A4XX_VBIF_ABIT_SORT_CONF				0x0000301d
+
+#define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
+
+#define REG_A4XX_VBIF_IN_RD_LIM_CONF0				0x0000302c
+
+#define REG_A4XX_VBIF_IN_RD_LIM_CONF1				0x0000302d
+
+#define REG_A4XX_VBIF_IN_WR_LIM_CONF0				0x00003030
+
+#define REG_A4XX_VBIF_IN_WR_LIM_CONF1				0x00003031
+
+#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB			0x00003049
+
+#define REG_A4XX_UNKNOWN_0CC5					0x00000cc5
+
+#define REG_A4XX_UNKNOWN_0CC6					0x00000cc6
+
+#define REG_A4XX_UNKNOWN_0D01					0x00000d01
+
+#define REG_A4XX_UNKNOWN_0E05					0x00000e05
+
+#define REG_A4XX_UNKNOWN_0E42					0x00000e42
+
+#define REG_A4XX_UNKNOWN_0EC2					0x00000ec2
+
+#define REG_A4XX_UNKNOWN_0EC3					0x00000ec3
+
+#define REG_A4XX_UNKNOWN_0F03					0x00000f03
+
+#define REG_A4XX_UNKNOWN_2001					0x00002001
+
+#define REG_A4XX_UNKNOWN_209B					0x0000209b
+
+#define REG_A4XX_UNKNOWN_20EF					0x000020ef
+
+#define REG_A4XX_UNKNOWN_20F0					0x000020f0
+
+#define REG_A4XX_UNKNOWN_20F1					0x000020f1
+
+#define REG_A4XX_UNKNOWN_20F2					0x000020f2
+
+#define REG_A4XX_UNKNOWN_20F3					0x000020f3
+
+#define REG_A4XX_UNKNOWN_20F4					0x000020f4
+
+#define REG_A4XX_UNKNOWN_20F5					0x000020f5
+
+#define REG_A4XX_UNKNOWN_20F6					0x000020f6
+
+#define REG_A4XX_UNKNOWN_20F7					0x000020f7
+
+#define REG_A4XX_UNKNOWN_2152					0x00002152
+
+#define REG_A4XX_UNKNOWN_2153					0x00002153
+
+#define REG_A4XX_UNKNOWN_2154					0x00002154
+
+#define REG_A4XX_UNKNOWN_2155					0x00002155
+
+#define REG_A4XX_UNKNOWN_2156					0x00002156
+
+#define REG_A4XX_UNKNOWN_2157					0x00002157
+
+#define REG_A4XX_UNKNOWN_21C3					0x000021c3
+
+#define REG_A4XX_UNKNOWN_21E6					0x000021e6
+
+#define REG_A4XX_UNKNOWN_2209					0x00002209
+
+#define REG_A4XX_UNKNOWN_22D7					0x000022d7
+
+#define REG_A4XX_TEX_SAMP_0					0x00000000
+
+#define REG_A4XX_TEX_SAMP_1					0x00000001
+#define A4XX_TEX_SAMP_1_MAX_LOD__MASK				0x000fff00
+#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT				8
+static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
+{
+	return ((((uint32_t)(val * 12.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT)
& A4XX_TEX_SAMP_1_MAX_LOD__MASK;
+}
+#define A4XX_TEX_SAMP_1_MIN_LOD__MASK				0xfff00000
+#define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT				20
+static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
+{
+	return ((((uint32_t)(val * 12.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT)
& A4XX_TEX_SAMP_1_MIN_LOD__MASK;
+}
+
+#define REG_A4XX_TEX_CONST_0					0x00000000
+#define A4XX_TEX_CONST_0_TILED					0x00000001
+#define A4XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
+#define A4XX_TEX_CONST_0_SWIZ_X__SHIFT				4
+static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
+{
+	return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) &
A4XX_TEX_CONST_0_SWIZ_X__MASK;
+}
+#define A4XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
+#define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT				7
+static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
+{
+	return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) &
A4XX_TEX_CONST_0_SWIZ_Y__MASK;
+}
+#define A4XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
+#define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT				10
+static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
+{
+	return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) &
A4XX_TEX_CONST_0_SWIZ_Z__MASK;
+}
+#define A4XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
+#define A4XX_TEX_CONST_0_SWIZ_W__SHIFT				13
+static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
+{
+	return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) &
A4XX_TEX_CONST_0_SWIZ_W__MASK;
+}
+#define A4XX_TEX_CONST_0_FMT__MASK				0x1fc00000
+#define A4XX_TEX_CONST_0_FMT__SHIFT				22
+static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
+{
+	return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) &
A4XX_TEX_CONST_0_FMT__MASK;
+}
+
+#define REG_A4XX_TEX_CONST_1					0x00000001
+#define A4XX_TEX_CONST_1_HEIGHT__MASK				0x00007fff
+#define A4XX_TEX_CONST_1_HEIGHT__SHIFT				0
+static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
+{
+	return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) &
A4XX_TEX_CONST_1_HEIGHT__MASK;
+}
+#define A4XX_TEX_CONST_1_WIDTH__MASK				0x1fff8000
+#define A4XX_TEX_CONST_1_WIDTH__SHIFT				15
+static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
+{
+	return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) &
A4XX_TEX_CONST_1_WIDTH__MASK;
+}
+
+#define REG_A4XX_TEX_CONST_2					0x00000002
+#define A4XX_TEX_CONST_2_PITCH__MASK				0x3ffffe00
+#define A4XX_TEX_CONST_2_PITCH__SHIFT				9
+static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
+{
+	return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) &
A4XX_TEX_CONST_2_PITCH__MASK;
+}
+
+
+#endif /* A4XX_XML */

[1/3] drm/msm: Additional definitions for a3xx and a4xx

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