From patchwork Thu Aug 6 01:27:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 6955181 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B09209F38B for ; Thu, 6 Aug 2015 01:27:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B534720675 for ; Thu, 6 Aug 2015 01:27:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9D06F20670 for ; Thu, 6 Aug 2015 01:27:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752682AbbHFB10 (ORCPT ); Wed, 5 Aug 2015 21:27:26 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:51615 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751305AbbHFB10 (ORCPT ); Wed, 5 Aug 2015 21:27:26 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 974A41405B7; Thu, 6 Aug 2015 01:27:25 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 684781402EC; Thu, 6 Aug 2015 01:27:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from [10.134.64.202] (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id AC4441402EC; Thu, 6 Aug 2015 01:27:24 +0000 (UTC) Message-ID: <55C2B7FC.5090402@codeaurora.org> Date: Wed, 05 Aug 2015 18:27:24 -0700 From: Stephen Boyd User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130329 Thunderbird/17.0.5 MIME-Version: 1.0 To: Kumar Gala CC: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, arm@kernel.org, Lina Iyer Subject: Re: [PATCH v5 2/2] firmware: qcom: scm: Add support for ARM64 SoCs References: <1430249038-30987-1-git-send-email-galak@codeaurora.org> <1430249038-30987-2-git-send-email-galak@codeaurora.org> In-Reply-To: <1430249038-30987-2-git-send-email-galak@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 04/28/2015 12:23 PM, Kumar Gala wrote: > + > +int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, > + u64 *ret1, u64 *ret2, u64 *ret3) > +{ > + register u64 r0 asm("r0") = x0; > + register u64 r1 asm("r1") = x1; > + register u64 r2 asm("r2") = x2; > + register u64 r3 asm("r3") = x3; > + register u64 r4 asm("r4") = x4; > + register u64 r5 asm("r5") = x5; This should set x6 to 0. register u32 r6 asm("r6") = 0; for example. > + > + do { > + asm volatile( > + __asmeq("%0", "x0") > + __asmeq("%1", "x1") > + __asmeq("%2", "x2") > + __asmeq("%3", "x3") > + __asmeq("%4", "x0") > + __asmeq("%5", "x1") > + __asmeq("%6", "x2") > + __asmeq("%7", "x3") > + __asmeq("%8", "x4") > + __asmeq("%9", "x5") And then the asmeq thing here for x6. > +#ifdef REQUIRES_SEC > + ".arch_extension sec\n" > +#endif > + "smc #0\n" > + : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) > + : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), > + "r" (r5) And add x6 as an input here. > + : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", and remove x6 as a clobber. > + "x14", "x15", "x16", "x17"); > + } while (r0 == QCOM_SCM_INTERRUPTED); > + > + if (ret1) > + *ret1 = r1; > + if (ret2) > + *ret2 = r2; > + if (ret3) > + *ret3 = r3; > + > + return r0; > +} > + > +int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, > + u64 *ret1, u64 *ret2, u64 *ret3) > +{ > + register u32 r0 asm("r0") = w0; > + register u32 r1 asm("r1") = w1; > + register u32 r2 asm("r2") = w2; > + register u32 r3 asm("r3") = w3; > + register u32 r4 asm("r4") = w4; > + register u32 r5 asm("r5") = w5; This needs to set r6 to 0 as well register u32 r6 asm("r6") = 0; for example. > + > + do { > + asm volatile( > + __asmeq("%0", "x0") > + __asmeq("%1", "x1") > + __asmeq("%2", "x2") > + __asmeq("%3", "x3") > + __asmeq("%4", "x0") > + __asmeq("%5", "x1") > + __asmeq("%6", "x2") > + __asmeq("%7", "x3") > + __asmeq("%8", "x4") > + __asmeq("%9", "x5") And then another asmeq thing here for x6. > +#ifdef REQUIRES_SEC > + ".arch_extension sec\n" > +#endif > + "smc #0\n" > + : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) > + : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), > + "r" (r5) And then add r6 here as an input > + : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", And remove r6 from the clobber. > + "x14", "x15", "x16", "x17"); > + > + } while (r0 == QCOM_SCM_INTERRUPTED); > + > + if (ret1) > + *ret1 = r1; > + if (ret2) > + *ret2 = r2; > + if (ret3) > + *ret3 = r3; > + > + return r0; > +} > + > Here's a totally untested patch for that. Signed-off-by: Stephen Boyd ----8<----- diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index a95fd9b5d576..8f7e65ff524c 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -114,6 +114,7 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, register u64 r3 asm("r3") = x3; register u64 r4 asm("r4") = x4; register u64 r5 asm("r5") = x5; + register u64 r6 asm("r5") = 0; do { asm volatile( @@ -127,14 +128,15 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, __asmeq("%7", "x3") __asmeq("%8", "x4") __asmeq("%9", "x5") + __asmeq("%10", "x6") #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0\n" : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), - "r" (r5) - : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", + "r" (r5), "r" (r6) + : "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); } while (r0 == QCOM_SCM_INTERRUPTED); @@ -157,6 +159,7 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, register u32 r3 asm("r3") = w3; register u32 r4 asm("r4") = w4; register u32 r5 asm("r5") = w5; + register u32 r6 asm("r6") = 0; do { asm volatile( @@ -170,14 +173,15 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, __asmeq("%7", "x3") __asmeq("%8", "x4") __asmeq("%9", "x5") + __asmeq("%10", "x6") #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0\n" : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), - "r" (r5) - : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", + "r" (r5), "r" (r6) + : "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); } while (r0 == QCOM_SCM_INTERRUPTED);