From patchwork Fri Sep 9 16:34:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Ramana X-Patchwork-Id: 9323959 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4E96660752 for ; Fri, 9 Sep 2016 16:34:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3F24429F78 for ; Fri, 9 Sep 2016 16:34:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 33BD429F7A; Fri, 9 Sep 2016 16:34:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF02F29F78 for ; Fri, 9 Sep 2016 16:34:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752115AbcIIQeL (ORCPT ); Fri, 9 Sep 2016 12:34:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:41711 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751121AbcIIQeL (ORCPT ); Fri, 9 Sep 2016 12:34:11 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 573AD617B8; Fri, 9 Sep 2016 16:34:10 +0000 (UTC) Received: from [10.204.78.108] (unknown [202.46.23.54]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: sramana@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D7CFD61D7C; Fri, 9 Sep 2016 16:34:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org D7CFD61D7C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=sramana@codeaurora.org Message-ID: <57D2E47D.5030105@codeaurora.org> Date: Fri, 09 Sep 2016 22:04:05 +0530 From: Srinivas Ramana User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130329 Thunderbird/17.0.5 MIME-Version: 1.0 To: linux@armlinux.org.uk, will.deacon@arm.com, nicolas.pitre@linaro.org CC: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Improper TTBCR for arm 32bit kernel decompression Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hello, While trying to boot arm-32 bit kernel, I came across a problem where TTBCR is in improper state. If the bootloader uses the long descriptor format and jumps to kernel decompressor code, TTBCR may not be in the right state. So, as soon as the MMU is enabled, execution can not proceed further. Before enabling the MMU, it is required to clear the TTBCR.PD0 field to use TTBR0 for translation table walks. Also, TTBCR.N should be reset to '0' to indicate the correct base address width. The 'commit dbece45894d3a ("ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores")' does the reset of TTBCR.N, but doesn't consider all the bits for the size of TTBCR.N. when i tried the below change where i explicitly clear TTBCR.PD0 and use correct mask for TTBCR.N, I see proper memory after MMU is enabled and decompression succeeds. Request your comments on the change below. If it looks good, I can submit a patch for inclusion. ---------------------8<---------------------------------- control mcrne p15, 0, r6, c2, c0, 2 @ load ttb control ---------------------8<---------------------------------- Thanks, -- Srinivas R diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index af11c2f..5769f1f 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -779,7 +779,8 @@ __armv7_mmu_cache_on: orrne r0, r0, #1 @ MMU enabled movne r1, #0xfffffffd @ domain 0 = client bic r6, r6, #1 << 31 @ 32-bit translation system - bic r6, r6, #3 << 0 @ use only ttbr0 + bic r6, r6, #7 << 0 @ width of base address field + bic r6, r6, #1 << 4 @ use only ttbr0 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access