| Message ID | 5a048452c128e4b678609bef780e2c1328c482fc.1637047731.git.quic_vamslank@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Pdc, GCC and RPMh clock support for SDX65 | expand |
On 15-11-21, 23:38, quic_vamslank@quicinc.com wrote: > From: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> > > Add a LUCID_EVO PLL type for SDX65 SoC from Qualcomm. > > Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> > --- > drivers/clk/qcom/clk-alpha-pll.c | 171 +++++++++++++++++++++++++++++++ > drivers/clk/qcom/clk-alpha-pll.h | 3 + > 2 files changed, 174 insertions(+) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index eaedcceb766f..b2dbb8d56773 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -1,5 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. This line should ideally come after the below line.. > * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. > */ > > @@ -139,6 +140,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { > [PLL_OFF_OPMODE] = 0x28, > [PLL_OFF_STATUS] = 0x38, > }, > + [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { > + [PLL_OFF_OPMODE] = 0x04, > + [PLL_OFF_STATUS] = 0x0c, > + [PLL_OFF_L_VAL] = 0x10, > + [PLL_OFF_ALPHA_VAL] = 0x14, > + [PLL_OFF_USER_CTL] = 0x18, > + [PLL_OFF_USER_CTL_U] = 0x1c, > + [PLL_OFF_CONFIG_CTL] = 0x20, > + [PLL_OFF_CONFIG_CTL_U] = 0x24, > + [PLL_OFF_CONFIG_CTL_U1] = 0x28, > + [PLL_OFF_TEST_CTL] = 0x2c, > + [PLL_OFF_TEST_CTL_U] = 0x30, > + [PLL_OFF_TEST_CTL_U1] = 0x34, > + }, > }; > EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > > @@ -175,6 +190,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) > #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) > > +/* LUCID EVO PLL specific settings and offsets */ > +#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) > +#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) > + > /* ZONDA PLL specific */ > #define ZONDA_PLL_OUT_MASK 0xf > #define ZONDA_STAY_IN_CFA BIT(16) > @@ -1951,3 +1970,155 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { > .set_rate = clk_zonda_pll_set_rate, > }; > EXPORT_SYMBOL(clk_alpha_pll_zonda_ops); > + > +static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > + struct regmap *regmap = pll->clkr.regmap; > + u32 val; > + int ret; > + > + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); > + if (ret) > + return ret; > + > + /* If in FSM mode, just vote for it */ > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { > + ret = clk_enable_regmap(hw); > + if (ret) > + return ret; > + return wait_for_pll_enable_lock(pll); > + } > + > + /* Check if PLL is already enabled */ > + ret = trion_pll_is_enabled(pll, regmap); > + if (ret < 0) > + return ret; > + else if (ret) { > + pr_warn("%s PLL is already enabled\n", > + clk_hw_get_name(&pll->clkr.hw)); this should fit in a single line > + return 0; > + } > + > + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); > + if (ret) > + return ret; > + > + /* Set operation mode to RUN */ > + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); > + > + ret = wait_for_pll_enable_lock(pll); > + if (ret) > + return ret; > + > + /* Enable the PLL outputs */ > + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); > + if (ret) > + return ret; > + > + /* Enable the global PLL outputs */ > + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); > + if (ret) > + return ret; > + > + /* Ensure that the write above goes through before returning. */ > + mb(); > + return ret; > +} > + > +static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > + struct regmap *regmap = pll->clkr.regmap; > + u32 val; > + int ret; > + > + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); > + if (ret) > + return; > + > + /* If in FSM mode, just unvote it */ > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { > + clk_disable_regmap(hw); > + return; > + } > + > + /* Disable the global PLL output */ > + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); > + if (ret) > + return; > + > + /* Disable the PLL outputs */ > + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); > + if (ret) > + return; > + > + /* Place the PLL mode in STANDBY */ > + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); > +} > + > +static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) pls align this to preceding line open brace > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > + struct regmap *regmap = pll->clkr.regmap; > + u32 l, frac; > + > + regmap_read(regmap, PLL_L_VAL(pll), &l); > + l &= LUCID_EVO_PLL_L_VAL_MASK; > + regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); > + > + return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); > +} I think this can use __alpha_pll_trion_set_rate() > + > +static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, > + unsigned long rate, unsigned long parent_rate) > +{ > + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); > + struct regmap *regmap = pll->clkr.regmap; > + int i, val, div, ret; > + > + /* > + * If the PLL is in FSM mode, then treat set_rate callback as a > + * no-operation. > + */ > + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); > + if (ret) > + return ret; > + > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) > + return 0; > + > + if (!pll->post_div_table) { > + pr_err("Missing the post_div_table for the PLL\n"); > + return -EINVAL; > + } > + > + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); > + for (i = 0; i < pll->num_post_div; i++) { > + if (pll->post_div_table[i].div == div) { > + val = pll->post_div_table[i].val; > + break; > + } > + } > + > + return regmap_update_bits(regmap, PLL_USER_CTL(pll), > + (BIT(pll->width) - 1) << pll->post_div_shift, > + val << pll->post_div_shift); > +} This looks _very_ similar to clk_lucid_5lpe_pll_postdiv_set_rate() maybe add a helper which both can use and pass on the LUCID_EVO_ENABLE_VOTE_RUN as argument to helper?
On Tue, Nov 16, 2021 at 01:55:29PM +0530, Vinod Koul wrote: > On 15-11-21, 23:38, quic_vamslank@quicinc.com wrote: > > From: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> > > > > Add a LUCID_EVO PLL type for SDX65 SoC from Qualcomm. > > > > Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> > > --- > > drivers/clk/qcom/clk-alpha-pll.c | 171 +++++++++++++++++++++++++++++++ > > drivers/clk/qcom/clk-alpha-pll.h | 3 + > > 2 files changed, 174 insertions(+) > > > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > > index eaedcceb766f..b2dbb8d56773 100644 > > --- a/drivers/clk/qcom/clk-alpha-pll.c > > +++ b/drivers/clk/qcom/clk-alpha-pll.c > > @@ -1,5 +1,6 @@ > > // SPDX-License-Identifier: GPL-2.0 > > /* > > + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. > > This line should ideally come after the below line.. Will do. > > > * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. > > */ > > > > @@ -139,6 +140,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { > > [PLL_OFF_OPMODE] = 0x28, > > [PLL_OFF_STATUS] = 0x38, > > }, > > + [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { > > + [PLL_OFF_OPMODE] = 0x04, > > + [PLL_OFF_STATUS] = 0x0c, > > + [PLL_OFF_L_VAL] = 0x10, > > + [PLL_OFF_ALPHA_VAL] = 0x14, > > + [PLL_OFF_USER_CTL] = 0x18, > > + [PLL_OFF_USER_CTL_U] = 0x1c, > > + [PLL_OFF_CONFIG_CTL] = 0x20, > > + [PLL_OFF_CONFIG_CTL_U] = 0x24, > > + [PLL_OFF_CONFIG_CTL_U1] = 0x28, > > + [PLL_OFF_TEST_CTL] = 0x2c, > > + [PLL_OFF_TEST_CTL_U] = 0x30, > > + [PLL_OFF_TEST_CTL_U1] = 0x34, > > + }, > > }; > > EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > > > > @@ -175,6 +190,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > > #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) > > #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) > > > > +/* LUCID EVO PLL specific settings and offsets */ > > +#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) > > +#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) > > + > > /* ZONDA PLL specific */ > > #define ZONDA_PLL_OUT_MASK 0xf > > #define ZONDA_STAY_IN_CFA BIT(16) > > @@ -1951,3 +1970,155 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { > > .set_rate = clk_zonda_pll_set_rate, > > }; > > EXPORT_SYMBOL(clk_alpha_pll_zonda_ops); > > + > > +static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) > > +{ > > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > > + struct regmap *regmap = pll->clkr.regmap; > > + u32 val; > > + int ret; > > + > > + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); > > + if (ret) > > + return ret; > > + > > + /* If in FSM mode, just vote for it */ > > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { > > + ret = clk_enable_regmap(hw); > > + if (ret) > > + return ret; > > + return wait_for_pll_enable_lock(pll); > > + } > > + > > + /* Check if PLL is already enabled */ > > + ret = trion_pll_is_enabled(pll, regmap); > > + if (ret < 0) > > + return ret; > > + else if (ret) { > > + pr_warn("%s PLL is already enabled\n", > > + clk_hw_get_name(&pll->clkr.hw)); > > this should fit in a single line Will do. > > > + return 0; > > + } > > + > > + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); > > + if (ret) > > + return ret; > > + > > + /* Set operation mode to RUN */ > > + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); > > + > > + ret = wait_for_pll_enable_lock(pll); > > + if (ret) > > + return ret; > > + > > + /* Enable the PLL outputs */ > > + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); > > + if (ret) > > + return ret; > > + > > + /* Enable the global PLL outputs */ > > + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); > > + if (ret) > > + return ret; > > + > > + /* Ensure that the write above goes through before returning. */ > > + mb(); > > + return ret; > > +} > > + > > +static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) > > +{ > > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > > + struct regmap *regmap = pll->clkr.regmap; > > + u32 val; > > + int ret; > > + > > + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); > > + if (ret) > > + return; > > + > > + /* If in FSM mode, just unvote it */ > > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { > > + clk_disable_regmap(hw); > > + return; > > + } > > + > > + /* Disable the global PLL output */ > > + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); > > + if (ret) > > + return; > > + > > + /* Disable the PLL outputs */ > > + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); > > + if (ret) > > + return; > > + > > + /* Place the PLL mode in STANDBY */ > > + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); > > +} > > + > > +static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, > > + unsigned long parent_rate) > > pls align this to preceding line open brace Will do. > > > +{ > > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > > + struct regmap *regmap = pll->clkr.regmap; > > + u32 l, frac; > > + > > + regmap_read(regmap, PLL_L_VAL(pll), &l); > > + l &= LUCID_EVO_PLL_L_VAL_MASK; > > + regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); > > + > > + return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); > > +} > > I think this can use __alpha_pll_trion_set_rate() I didn't get with which function are you comparing this. I cannot able to find any function similar to this. > > > + > > +static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, > > + unsigned long rate, unsigned long parent_rate) > > +{ > > + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); > > + struct regmap *regmap = pll->clkr.regmap; > > + int i, val, div, ret; > > + > > + /* > > + * If the PLL is in FSM mode, then treat set_rate callback as a > > + * no-operation. > > + */ > > + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); > > + if (ret) > > + return ret; > > + > > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) > > + return 0; > > + > > + if (!pll->post_div_table) { > > + pr_err("Missing the post_div_table for the PLL\n"); > > + return -EINVAL; > > + } > > + > > + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); > > + for (i = 0; i < pll->num_post_div; i++) { > > + if (pll->post_div_table[i].div == div) { > > + val = pll->post_div_table[i].val; > > + break; > > + } > > + } > > + > > + return regmap_update_bits(regmap, PLL_USER_CTL(pll), > > + (BIT(pll->width) - 1) << pll->post_div_shift, > > + val << pll->post_div_shift); > > +} > > This looks _very_ similar to clk_lucid_5lpe_pll_postdiv_set_rate() maybe > add a helper which both can use and pass on the > LUCID_EVO_ENABLE_VOTE_RUN as argument to helper? That's a good thought. I can do that. > > -- > ~Vinod
On 17-11-21, 17:54, Vamsi Krishna Lanka wrote: > On Tue, Nov 16, 2021 at 01:55:29PM +0530, Vinod Koul wrote: > > On 15-11-21, 23:38, quic_vamslank@quicinc.com wrote: > > > From: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> > > > +{ > > > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > > > + struct regmap *regmap = pll->clkr.regmap; > > > + u32 l, frac; > > > + > > > + regmap_read(regmap, PLL_L_VAL(pll), &l); > > > + l &= LUCID_EVO_PLL_L_VAL_MASK; > > > + regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); > > > + > > > + return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); > > > +} > > > > I think this can use __alpha_pll_trion_set_rate() > > I didn't get with which function are you comparing this. I cannot able to > find any function similar to this. This is in upstream, pls see commit: 80ca7765fc75 ("clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate()")
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index eaedcceb766f..b2dbb8d56773 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ @@ -139,6 +140,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_OPMODE] = 0x28, [PLL_OFF_STATUS] = 0x38, }, + [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { + [PLL_OFF_OPMODE] = 0x04, + [PLL_OFF_STATUS] = 0x0c, + [PLL_OFF_L_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL] = 0x14, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0x1c, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_CONFIG_CTL_U1] = 0x28, + [PLL_OFF_TEST_CTL] = 0x2c, + [PLL_OFF_TEST_CTL_U] = 0x30, + [PLL_OFF_TEST_CTL_U1] = 0x34, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -175,6 +190,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) +/* LUCID EVO PLL specific settings and offsets */ +#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) +#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) + /* ZONDA PLL specific */ #define ZONDA_PLL_OUT_MASK 0xf #define ZONDA_STAY_IN_CFA BIT(16) @@ -1951,3 +1970,155 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { .set_rate = clk_zonda_pll_set_rate, }; EXPORT_SYMBOL(clk_alpha_pll_zonda_ops); + +static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct regmap *regmap = pll->clkr.regmap; + u32 val; + int ret; + + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); + if (ret) + return ret; + + /* If in FSM mode, just vote for it */ + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { + ret = clk_enable_regmap(hw); + if (ret) + return ret; + return wait_for_pll_enable_lock(pll); + } + + /* Check if PLL is already enabled */ + ret = trion_pll_is_enabled(pll, regmap); + if (ret < 0) + return ret; + else if (ret) { + pr_warn("%s PLL is already enabled\n", + clk_hw_get_name(&pll->clkr.hw)); + return 0; + } + + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); + if (ret) + return ret; + + /* Set operation mode to RUN */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); + + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + + /* Enable the PLL outputs */ + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); + if (ret) + return ret; + + /* Enable the global PLL outputs */ + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); + if (ret) + return ret; + + /* Ensure that the write above goes through before returning. */ + mb(); + return ret; +} + +static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct regmap *regmap = pll->clkr.regmap; + u32 val; + int ret; + + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); + if (ret) + return; + + /* If in FSM mode, just unvote it */ + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { + clk_disable_regmap(hw); + return; + } + + /* Disable the global PLL output */ + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + if (ret) + return; + + /* Disable the PLL outputs */ + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); + if (ret) + return; + + /* Place the PLL mode in STANDBY */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); +} + +static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct regmap *regmap = pll->clkr.regmap; + u32 l, frac; + + regmap_read(regmap, PLL_L_VAL(pll), &l); + l &= LUCID_EVO_PLL_L_VAL_MASK; + regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); + + return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); +} + +static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + struct regmap *regmap = pll->clkr.regmap; + int i, val, div, ret; + + /* + * If the PLL is in FSM mode, then treat set_rate callback as a + * no-operation. + */ + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); + if (ret) + return ret; + + if (val & LUCID_EVO_ENABLE_VOTE_RUN) + return 0; + + if (!pll->post_div_table) { + pr_err("Missing the post_div_table for the PLL\n"); + return -EINVAL; + } + + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + for (i = 0; i < pll->num_post_div; i++) { + if (pll->post_div_table[i].div == div) { + val = pll->post_div_table[i].val; + break; + } + } + + return regmap_update_bits(regmap, PLL_USER_CTL(pll), + (BIT(pll->width) - 1) << pll->post_div_shift, + val << pll->post_div_shift); +} + +const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { + .enable = alpha_pll_lucid_evo_enable, + .disable = alpha_pll_lucid_evo_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = alpha_pll_lucid_evo_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); + +const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, + .set_rate = clk_lucid_evo_pll_postdiv_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 55e4fa47912f..6e9907deaf30 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -17,6 +17,7 @@ enum { CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, + CLK_ALPHA_PLL_TYPE_LUCID_EVO, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -151,6 +152,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_zonda_ops; #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops +extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; +extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config);