| Message ID | 8c5ff297d8c89d9d451352f189baf26c8938842a.1591708204.git.saiprakash.ranjan@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add coresight support for SM8150 and few changes to SC7180 | expand |
On Tue, Jun 09, 2020 at 07:00:28PM +0530, Sai Prakash Ranjan wrote: > Add "qcom,skip-power-up" property to skip powering up ETM > on SC7180 SoC to workaround a hardware errata where CPU > watchdog counter is stopped when ETM power up bit is set > (i.e., when TRCPDCR.PU = 1). > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > > Depends on ETM driver change here: > - https://git.linaro.org/kernel/coresight.git/commit/?h=next-v5.8-rc1&id=159e248e75b1b548276b6571d7740a35cab1f5be > > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 7c2b79dda3d7..f684a0b87848 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -1810,6 +1810,7 @@ > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > arm,coresight-loses-context-with-cpu; > + qcom,skip-power-up; > > out-ports { > port { > @@ -1829,6 +1830,7 @@ > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > arm,coresight-loses-context-with-cpu; > + qcom,skip-power-up; > > out-ports { > port { > @@ -1848,6 +1850,7 @@ > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > arm,coresight-loses-context-with-cpu; > + qcom,skip-power-up; > > out-ports { > port { > @@ -1867,6 +1870,7 @@ > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > arm,coresight-loses-context-with-cpu; > + qcom,skip-power-up; > > out-ports { > port { > @@ -1886,6 +1890,7 @@ > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > arm,coresight-loses-context-with-cpu; > + qcom,skip-power-up; > > out-ports { > port { > @@ -1905,6 +1910,7 @@ > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > arm,coresight-loses-context-with-cpu; > + qcom,skip-power-up; > > out-ports { > port { > @@ -1924,6 +1930,7 @@ > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > arm,coresight-loses-context-with-cpu; > + qcom,skip-power-up; > > out-ports { > port { > @@ -1943,6 +1950,7 @@ > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > arm,coresight-loses-context-with-cpu; > + qcom,skip-power-up; Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > > out-ports { > port { > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 7c2b79dda3d7..f684a0b87848 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1810,6 +1810,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1829,6 +1830,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1848,6 +1850,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1867,6 +1870,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1886,6 +1890,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1905,6 +1910,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1924,6 +1930,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -1943,6 +1950,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port {
Add "qcom,skip-power-up" property to skip powering up ETM on SC7180 SoC to workaround a hardware errata where CPU watchdog counter is stopped when ETM power up bit is set (i.e., when TRCPDCR.PU = 1). Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> --- Depends on ETM driver change here: - https://git.linaro.org/kernel/coresight.git/commit/?h=next-v5.8-rc1&id=159e248e75b1b548276b6571d7740a35cab1f5be --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)