diff mbox series

[PATCHv10,4/6] drm/meson: Fix overflow implicit truncation warnings

Message ID 9c7ff199d826b60e019c0eeeb6aa280abfdb9a82.1644824638.git.quic_saipraka@quicinc.com (mailing list archive)
State Superseded
Headers show
Series lib/rwmmio/arm64: Add support to trace register reads/writes | expand

Commit Message

Sai Prakash Ranjan Feb. 24, 2022, 6:07 a.m. UTC
Fix -Woverflow warnings for drm/meson driver which is a result
of moving arm64 custom MMIO accessor macros to asm-generic function
implementations giving a bonus type-checking now and uncovering these
overflow warnings.

drivers/gpu/drm/meson/meson_viu.c: In function ‘meson_viu_init’:
drivers/gpu/drm/meson/meson_registers.h:1826:48: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
 #define  VIU_OSD_BLEND_REORDER(dest, src)      ((src) << (dest * 4))
                                                ^
drivers/gpu/drm/meson/meson_viu.c:472:18: note: in expansion of macro ‘VIU_OSD_BLEND_REORDER’
   writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
                  ^~~~~~~~~~~~~~~~~~~~~

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
 drivers/gpu/drm/meson/meson_viu.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

Comments

Arnd Bergmann April 27, 2022, 3:59 p.m. UTC | #1
On Thu, Feb 24, 2022 at 7:07 AM Sai Prakash Ranjan
<quic_saipraka@quicinc.com> wrote:
>
> Fix -Woverflow warnings for drm/meson driver which is a result
> of moving arm64 custom MMIO accessor macros to asm-generic function
> implementations giving a bonus type-checking now and uncovering these
> overflow warnings.
>
> drivers/gpu/drm/meson/meson_viu.c: In function ‘meson_viu_init’:
> drivers/gpu/drm/meson/meson_registers.h:1826:48: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
>  #define  VIU_OSD_BLEND_REORDER(dest, src)      ((src) << (dest * 4))
>                                                 ^
> drivers/gpu/drm/meson/meson_viu.c:472:18: note: in expansion of macro ‘VIU_OSD_BLEND_REORDER’
>    writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
>                   ^~~~~~~~~~~~~~~~~~~~~
>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Neil Armstrong <narmstrong@baylibre.com>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>

Reviewed-by: Arnd Bergmann <arnd@arndb.de>

It took me a bit to understand why we got the warning in the first place, but I
should have just read the patch description, it's all there....
Sai Prakash Ranjan April 28, 2022, 3:03 a.m. UTC | #2
On 4/27/2022 9:29 PM, Arnd Bergmann wrote:
> On Thu, Feb 24, 2022 at 7:07 AM Sai Prakash Ranjan
> <quic_saipraka@quicinc.com> wrote:
>> Fix -Woverflow warnings for drm/meson driver which is a result
>> of moving arm64 custom MMIO accessor macros to asm-generic function
>> implementations giving a bonus type-checking now and uncovering these
>> overflow warnings.
>>
>> drivers/gpu/drm/meson/meson_viu.c: In function ‘meson_viu_init’:
>> drivers/gpu/drm/meson/meson_registers.h:1826:48: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
>>   #define  VIU_OSD_BLEND_REORDER(dest, src)      ((src) << (dest * 4))
>>                                                  ^
>> drivers/gpu/drm/meson/meson_viu.c:472:18: note: in expansion of macro ‘VIU_OSD_BLEND_REORDER’
>>     writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
>>                    ^~~~~~~~~~~~~~~~~~~~~
>>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Neil Armstrong <narmstrong@baylibre.com>
>> Reported-by: kernel test robot <lkp@intel.com>
>> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>
> It took me a bit to understand why we got the warning in the first place, but I
> should have just read the patch description, it's all there....

Right :)

Thanks,
Sai
diff mbox series

Patch

diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index 259f3e6bec90..bb7e109534de 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -469,17 +469,17 @@  void meson_viu_init(struct meson_drm *priv)
 			priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
 
 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
-		writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
-			       VIU_OSD_BLEND_REORDER(1, 0) |
-			       VIU_OSD_BLEND_REORDER(2, 0) |
-			       VIU_OSD_BLEND_REORDER(3, 0) |
-			       VIU_OSD_BLEND_DIN_EN(1) |
-			       VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
-			       VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
-			       VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
-			       VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
-			       VIU_OSD_BLEND_HOLD_LINES(4),
-			       priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
+		u32 val = (u32)VIU_OSD_BLEND_REORDER(0, 1) |
+			  (u32)VIU_OSD_BLEND_REORDER(1, 0) |
+			  (u32)VIU_OSD_BLEND_REORDER(2, 0) |
+			  (u32)VIU_OSD_BLEND_REORDER(3, 0) |
+			  (u32)VIU_OSD_BLEND_DIN_EN(1) |
+			  (u32)VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
+			  (u32)VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
+			  (u32)VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
+			  (u32)VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
+			  (u32)VIU_OSD_BLEND_HOLD_LINES(4);
+		writel_relaxed(val, priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
 
 		writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
 			       priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));