| Message ID | c2fca6c7-2421-42b4-a43d-68b251daf9b4@freebox.fr (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for qcom msm8998-venus (HW vdec / venc) | expand |
On 5/7/2024 2:59 PM, Marc Gonzalez wrote: > From: Pierre-Hugues Husson <phhusson@freebox.fr> > > Now that the venus clocks are fixed, we can add the DT node. > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > Signed-off-by: Pierre-Hugues Husson <phhusson@freebox.fr> > Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> > --- > arch/arm64/boot/dts/qcom/msm8998.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi > index 5f5b90a6e2bf1..3d3b1f61c0690 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi > @@ -3010,6 +3010,54 @@ mdss_dsi1_phy: phy@c996400 { > }; > }; > > + venus: video-codec@cc00000 { > + compatible = "qcom,msm8998-venus"; > + reg = <0x0cc00000 0xff000>; > + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&mmcc VIDEO_TOP_GDSC>; > + clocks = <&mmcc VIDEO_CORE_CLK>, > + <&mmcc VIDEO_AHB_CLK>, > + <&mmcc VIDEO_AXI_CLK>, > + <&mmcc VIDEO_MAXI_CLK>; > + clock-names = "core", "iface", "bus", "mbus"; > + iommus = <&mmss_smmu 0x400>, > + <&mmss_smmu 0x401>, > + <&mmss_smmu 0x40a>, > + <&mmss_smmu 0x407>, > + <&mmss_smmu 0x40e>, > + <&mmss_smmu 0x40f>, > + <&mmss_smmu 0x408>, > + <&mmss_smmu 0x409>, > + <&mmss_smmu 0x40b>, > + <&mmss_smmu 0x40c>, > + <&mmss_smmu 0x40d>, > + <&mmss_smmu 0x410>, > + <&mmss_smmu 0x421>, > + <&mmss_smmu 0x428>, > + <&mmss_smmu 0x429>, > + <&mmss_smmu 0x42b>, > + <&mmss_smmu 0x42c>, > + <&mmss_smmu 0x42d>, > + <&mmss_smmu 0x411>, > + <&mmss_smmu 0x431>; > + memory-region = <&venus_mem>; > + status = "disabled"; > + > + video-decoder { > + compatible = "venus-decoder"; > + clocks = <&mmcc VIDEO_SUBCORE0_CLK>; > + clock-names = "core"; > + power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>; > + }; > + > + video-encoder { > + compatible = "venus-encoder"; > + clocks = <&mmcc VIDEO_SUBCORE1_CLK>; > + clock-names = "core"; > + power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>; > + }; > + }; > + > mmss_smmu: iommu@cd00000 { > compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; > reg = <0x0cd00000 0x40000>; Acked-by: Vikash Garodia <quic_vgarodia@quicinc.com> Regards, Vikash
On 07/05/2024 11:29, Marc Gonzalez wrote: > From: Pierre-Hugues Husson <phhusson@freebox.fr> > > Now that the venus clocks are fixed, we can add the DT node. > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > Signed-off-by: Pierre-Hugues Husson <phhusson@freebox.fr> > Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> > --- > arch/arm64/boot/dts/qcom/msm8998.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi > index 5f5b90a6e2bf1..3d3b1f61c0690 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi > @@ -3010,6 +3010,54 @@ mdss_dsi1_phy: phy@c996400 { > }; > }; > > + venus: video-codec@cc00000 { > + compatible = "qcom,msm8998-venus"; > + reg = <0x0cc00000 0xff000>; > + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&mmcc VIDEO_TOP_GDSC>; > + clocks = <&mmcc VIDEO_CORE_CLK>, > + <&mmcc VIDEO_AHB_CLK>, > + <&mmcc VIDEO_AXI_CLK>, > + <&mmcc VIDEO_MAXI_CLK>; > + clock-names = "core", "iface", "bus", "mbus"; > + iommus = <&mmss_smmu 0x400>, > + <&mmss_smmu 0x401>, > + <&mmss_smmu 0x40a>, > + <&mmss_smmu 0x407>, > + <&mmss_smmu 0x40e>, > + <&mmss_smmu 0x40f>, > + <&mmss_smmu 0x408>, > + <&mmss_smmu 0x409>, > + <&mmss_smmu 0x40b>, > + <&mmss_smmu 0x40c>, > + <&mmss_smmu 0x40d>, > + <&mmss_smmu 0x410>, > + <&mmss_smmu 0x421>, > + <&mmss_smmu 0x428>, > + <&mmss_smmu 0x429>, > + <&mmss_smmu 0x42b>, > + <&mmss_smmu 0x42c>, > + <&mmss_smmu 0x42d>, > + <&mmss_smmu 0x411>, > + <&mmss_smmu 0x431>; > + memory-region = <&venus_mem>; > + status = "disabled"; > + > + video-decoder { > + compatible = "venus-decoder"; > + clocks = <&mmcc VIDEO_SUBCORE0_CLK>; > + clock-names = "core"; > + power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>; > + }; > + > + video-encoder { > + compatible = "venus-encoder"; > + clocks = <&mmcc VIDEO_SUBCORE1_CLK>; > + clock-names = "core"; > + power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>; > + }; > + }; > + > mmss_smmu: iommu@cd00000 { > compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; > reg = <0x0cd00000 0x40000>; Hello Bjorn, This patch is supposed to be merged through one of your trees, right? Regards
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 5f5b90a6e2bf1..3d3b1f61c0690 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3010,6 +3010,54 @@ mdss_dsi1_phy: phy@c996400 { }; }; + venus: video-codec@cc00000 { + compatible = "qcom,msm8998-venus"; + reg = <0x0cc00000 0xff000>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mmcc VIDEO_TOP_GDSC>; + clocks = <&mmcc VIDEO_CORE_CLK>, + <&mmcc VIDEO_AHB_CLK>, + <&mmcc VIDEO_AXI_CLK>, + <&mmcc VIDEO_MAXI_CLK>; + clock-names = "core", "iface", "bus", "mbus"; + iommus = <&mmss_smmu 0x400>, + <&mmss_smmu 0x401>, + <&mmss_smmu 0x40a>, + <&mmss_smmu 0x407>, + <&mmss_smmu 0x40e>, + <&mmss_smmu 0x40f>, + <&mmss_smmu 0x408>, + <&mmss_smmu 0x409>, + <&mmss_smmu 0x40b>, + <&mmss_smmu 0x40c>, + <&mmss_smmu 0x40d>, + <&mmss_smmu 0x410>, + <&mmss_smmu 0x421>, + <&mmss_smmu 0x428>, + <&mmss_smmu 0x429>, + <&mmss_smmu 0x42b>, + <&mmss_smmu 0x42c>, + <&mmss_smmu 0x42d>, + <&mmss_smmu 0x411>, + <&mmss_smmu 0x431>; + memory-region = <&venus_mem>; + status = "disabled"; + + video-decoder { + compatible = "venus-decoder"; + clocks = <&mmcc VIDEO_SUBCORE0_CLK>; + clock-names = "core"; + power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>; + }; + + video-encoder { + compatible = "venus-encoder"; + clocks = <&mmcc VIDEO_SUBCORE1_CLK>; + clock-names = "core"; + power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>; + }; + }; + mmss_smmu: iommu@cd00000 { compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; reg = <0x0cd00000 0x40000>;