From patchwork Thu Mar 30 08:40:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13193613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A11AC77B6F for ; Thu, 30 Mar 2023 08:42:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230355AbjC3Iml (ORCPT ); Thu, 30 Mar 2023 04:42:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229894AbjC3ImV (ORCPT ); Thu, 30 Mar 2023 04:42:21 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F5507EC3; Thu, 30 Mar 2023 01:41:57 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32U4fxlL008168; Thu, 30 Mar 2023 08:41:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=iHw8LdvkTxJ7oL9FR2QESLEXP/Mnvfxs0JR83t7NMks=; b=Fu3wm3WrZqsPuduK0ac56F2tR93Ei2zF3j++TCdrXw1exjtF1t65eassUr1PmCnGYzJ/ Nbfzj+e/kpN0UOPcMtCdym4DuXkOg/ufvERt0kJ92S8utztPDvscWjz6P0bipN4hBW5n vQwuFE3qSG33/ixJYueAv0wNd2mBLUaljf6TZI8mAbiHGnEEnM/f0RVARIzM9ZXpL19x iUC3AF5rAUw4UZnI8Ni7UsVtWw+0cWvAiKIrhiKK4MoVKZwvGjCHJGDC7LJTsksNmnmb jPIVzAdky15WD4nrckJGrtJRPZYWuWZkzKttDIDfIOxk8slWSSdbR92lBWb8V0PmL4CU rQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pn3mf8qx3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 08:41:44 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32U8fik1001521 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 08:41:44 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 30 Mar 2023 01:41:38 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes Date: Thu, 30 Mar 2023 14:10:49 +0530 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 5Jlno8a4bpNsiWBTkzci0WI_gi9chG5W X-Proofpoint-GUID: 5Jlno8a4bpNsiWBTkzci0WI_gi9chG5W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_04,2023-03-30_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 bulkscore=0 mlxscore=0 suspectscore=0 spamscore=0 adultscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303300069 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add USB phy and controller related nodes Signed-off-by: Varadarajan Narayanan --- Changes in v5: - Fix additional comments - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml - 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml Changes in v4: - Use newer bindings without subnodes - Fix coding style issues Changes in v3: - Insert the nodes at proper location Changes in v2: - Fixed issues flagged by Krzysztof - Fix issues reported by make dtbs_check - Remove NOC related clocks (to be added with proper interconnect support) Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 120 ++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 2bb4053..8fa9e1a 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -186,6 +186,33 @@ method = "smc"; }; + reg_usb_3p3: s3300 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "usb-phy-vdd-dummy"; + }; + + reg_usb_1p8: s1800 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "usb-phy-pll-dummy"; + }; + + reg_usb_0p925: s0925 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "usb-phy-dummy"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -215,6 +242,52 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + qusb_phy_0: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board_clk>; + clock-names = "cfg_ahb", + "ref"; + + vdd-supply = <®_usb_0p925>; + vdda-pll-supply = <®_usb_1p8>; + vdda-phy-dpdm-supply = <®_usb_3p3>; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + ssphy_0: phy@7d000 { + compatible = "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0007d000 0xa00>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&xo_board_clk>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + vdda-pll-supply = <®_usb_1p8>; + vdda-phy-supply = <®_usb_0p925>; + + status = "disabled"; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk"; + }; + pcie0_phy: phy@84000 { compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x00084000 0x1bc>; /* Serdes PLL */ @@ -436,6 +509,53 @@ status = "disabled"; }; + usb3: usb@8a00000 { + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_ANOC_USB_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "sys_noc_axi", + "anoc_axi", + "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event"; + + resets = <&gcc GCC_USB_BCR>; + status = "disabled"; + + dwc_0: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xcd00>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = ; + phys = <&qusb_phy_0>, <&ssphy_0>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */