| Message ID | cd3633a4-1781-0998-794d-d609daa9a89b@free.fr (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v1] arm64: dts: qcom: msm8998: Add PCIe PHY node | expand |
Bjorn, Please ignore this patch, it has been superseded by the series: [PATCH v1 0/3] PCIe and AR8151 on APQ8098/MSM8998 Regards. On 25/03/2019 18:37, Marc Gonzalez wrote: > Add MSM8998 PCIe QMP PHY DT node. > > Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> > --- > arch/arm64/boot/dts/qcom/msm8998.dtsi | 39 +++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi > index f9a922fdae75..8344ed1bf08d 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi > @@ -606,6 +606,45 @@ > #thermal-sensor-cells = <1>; > }; > > + phy@1c06000 { > + compatible = "qcom,msm8998-qmp-pcie-phy"; > + reg = <0x01c06000 0x18c>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clock-names = > + "aux", > + "cfg_ahb", > + "ref"; > + clocks = > + <&gcc GCC_PCIE_PHY_AUX_CLK>, > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_CLKREF_CLK>; > + > + reset-names = > + "phy", > + "common", > + "cfg"; > + resets = > + <&gcc GCC_PCIE_PHY_BCR>, > + <&gcc GCC_PCIE_PHY_COM_BCR>, > + <&gcc GCC_PCIE_PHY_NOCSR_COM_PHY_BCR>; > + > + vdda-phy-supply = <&vreg_l1a_0p875>; > + vdda-pll-supply = <&vreg_l2a_1p2>; > + > + pciephy: lane@1c06800 { > + reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; > + #phy-cells = <0>; > + > + clock-names = "pipe0"; > + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; > + clock-output-names = "pcie_0_pipe_clk_src"; > + #clock-cells = <0>; > + }; > + }; > + > tcsr_mutex_regs: syscon@1f40000 { > compatible = "syscon"; > reg = <0x1f40000 0x20000>; >
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index f9a922fdae75..8344ed1bf08d 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -606,6 +606,45 @@ #thermal-sensor-cells = <1>; }; + phy@1c06000 { + compatible = "qcom,msm8998-qmp-pcie-phy"; + reg = <0x01c06000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clock-names = + "aux", + "cfg_ahb", + "ref"; + clocks = + <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>; + + reset-names = + "phy", + "common", + "cfg"; + resets = + <&gcc GCC_PCIE_PHY_BCR>, + <&gcc GCC_PCIE_PHY_COM_BCR>, + <&gcc GCC_PCIE_PHY_NOCSR_COM_PHY_BCR>; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + + pciephy: lane@1c06800 { + reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; + #phy-cells = <0>; + + clock-names = "pipe0"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-output-names = "pcie_0_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>;
Add MSM8998 PCIe QMP PHY DT node. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 39 +++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)