From patchwork Thu Aug 9 12:32:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10561349 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 12BB113AC for ; Thu, 9 Aug 2018 12:33:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F3B182624C for ; Thu, 9 Aug 2018 12:33:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E78D02787C; Thu, 9 Aug 2018 12:33:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75FA02624C for ; Thu, 9 Aug 2018 12:33:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731985AbeHIO5l (ORCPT ); Thu, 9 Aug 2018 10:57:41 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:44544 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731969AbeHIO5k (ORCPT ); Thu, 9 Aug 2018 10:57:40 -0400 Received: by mail-pg1-f196.google.com with SMTP id r1-v6so2681938pgp.11 for ; Thu, 09 Aug 2018 05:32:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=zyKbfUOB0Y9T8bByL2E46QXLNpmRHMe5dD12vKApofY=; b=EUbM4/SIh7RAHxEjlJgTq6apupexB9/sDI3QO/YPngFPr1iC4TZjnKT5uHU6TgXbuq Dl54WWuhj2nbaU1XD6L0VEmkEMb+nW0TmZayNnpC5aMQIzPfP7O4XdQmGSix83xM7Sh+ Ur517vJlbwHPuKQVBIb5oughoqod27z2WwCT8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=zyKbfUOB0Y9T8bByL2E46QXLNpmRHMe5dD12vKApofY=; b=a/Hnb4PRRj+BlGWhNP6nwvwWgGjBOHQ5A3SnybalO0kWrtU10q6PdnNB1SsW2km2cD wS/gLPIir8Z7mKw/uL80VMTvVpv+4GH3wkM4cx0TSgCB8haopQhR+ul6R6pUBNmEhtDq n/97G6HmwMc+9g4ybh4RprMwgwRjjFnH7RhexiEwC6Pr+xLEW0z7IpvLOLmDx1obdz8M TW5E6jM8Qsd9E34SzDqHaYLKcBFVqwNAWVdc8GvqfP9DUBU3oKGeCcOjk/GGLFSlO7Fo 0zzyxEmkj2qsML9KJm4Gazg2ZpG3jpfVYg8qs4dEiBnpnvg1a+FWeam3fRu+H0VusbkO A6Dg== X-Gm-Message-State: AOUpUlEfytLtKvxLlCspy/3uQQHKJmtXdywlXbJNBBzlaHRMri6P65V9 2fb3A0E6pCNH/JfFbGDqTT8dtw== X-Google-Smtp-Source: AA+uWPynNbgSQQ9l/E1L3209WPLgCT7lV5BhDtWZ/Il0/Cm1U8gFwDoKDqPAPWZltPnd5jdW8qvJ1g== X-Received: by 2002:a63:8f03:: with SMTP id n3-v6mr2051619pgd.166.1533817978957; Thu, 09 Aug 2018 05:32:58 -0700 (PDT) Received: from localhost ([45.113.251.134]) by smtp.gmail.com with ESMTPSA id r1-v6sm20812005pfi.17.2018.08.09.05.32.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Aug 2018 05:32:58 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, David Brown , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Zhang Rui , linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org Subject: [PATCH v1 01/10] arm/arm64: dts: msm8974/msm8916: thermal: Split address space into two Date: Thu, 9 Aug 2018 18:02:33 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for the remaining platforms that have a similar register layout and make corresponding changes to the get_temp_common() function used by these platforms. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 ++++-- drivers/thermal/qcom/tsens-common.c | 5 +++-- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index d9019a49b292..3c4b81c29798 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -427,11 +427,13 @@ }; }; - tsens: thermal-sensor@fc4a8000 { + tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; + #qcom,sensors = <11>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index cc1040eacdf5..abf84df5a7bc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -774,11 +774,13 @@ }; }; - tsens: thermal-sensor@4a8000 { + tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens"; - reg = <0x4a8000 0x2000>; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; + #qcom,sensors = <5>; #thermal-sensor-cells = <1>; }; diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 6207d8d92351..478739543bbc 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -21,7 +21,7 @@ #include #include "tsens.h" -#define S0_ST_ADDR 0x1030 +#define STATUS_OFFSET 0x30 #define SN_ADDR_OFFSET 0x4 #define SN_ST_TEMP_MASK 0x3ff #define CAL_DEGC_PT1 30 @@ -107,8 +107,9 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp) unsigned int status_reg; int last_temp = 0, ret; - status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET; + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * SN_ADDR_OFFSET; ret = regmap_read(tmdev->map, status_reg, &code); + if (ret) return ret; last_temp = code & SN_ST_TEMP_MASK;