| Message ID | d183a99d-6fd7-8b06-3f22-a26415cf4967@free.fr (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | UFS on APQ8098 | expand |
On 1/16/2019 3:56 AM, Marc Gonzalez wrote: > Add host controller and PHY DT nodes. > > Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> > --- > TODO: check whether the driver uses the 'resets' prop > --- > arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 20 +++++++ > arch/arm64/boot/dts/qcom/msm8998.dtsi | 63 +++++++++++++++++++++++ > 2 files changed, 83 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi > index 50e9033aa7f6..cd1c9e84eab7 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi > @@ -257,3 +257,23 @@ > pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; > pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; > }; > + > +&ufshc { > + vdd-hba-fixed-regulator; Since we are not specifying the vdd anymore, I suspect this should be dropped. Do you know of any reason why we'd still need it? > + vcc-supply = <&vreg_l20a_2p95>; > + vccq-supply = <&vreg_l26a_1p2>; > + vccq2-supply = <&vreg_s4a_1p8>; > + vcc-max-microamp = <750000>; > + vccq-max-microamp = <560000>; > + vccq2-max-microamp = <750000>; > +}; > + > +&ufsphy { > + vdda-phy-supply = <&vreg_l1a_0p875>; > + vdda-pll-supply = <&vreg_l2a_1p2>; > + vddp-ref-clk-supply = <&vreg_l26a_1p2>; > + vdda-phy-max-microamp = <51400>; > + vdda-pll-max-microamp = <14600>; > + vddp-ref-clk-max-microamp = <100>; > + vddp-ref-clk-always-on; > +}; > diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi > index 6f4f4b79853b..36fd2e614464 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi > @@ -711,6 +711,69 @@ > redistributor-stride = <0x0 0x20000>; > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > }; > + > + ufshc: ufshc@1da4000 { > + compatible = "qcom,msm8998-ufshc", "qcom,ufshc", > + "jedec,ufs-2.0"; > + reg = <0x1da4000 0x2500>; Bjorn would like it if reg addresses are full width, ie 0x01da4000 > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&ufsphy_lanes>; > + phy-names = "ufsphy"; > + lanes-per-direction = <2>; > + power-domains = <&gcc UFS_GDSC>; > + > + clock-names = > + "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + clocks = > + <&gcc GCC_UFS_AXI_CLK>, > + <&gcc GCC_AGGRE1_UFS_AXI_CLK>, > + <&gcc GCC_UFS_AHB_CLK>, > + <&gcc GCC_UFS_UNIPRO_CORE_CLK>, > + <&rpmcc RPM_SMD_LN_BB_CLK1>, > + <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; > + freq-table-hz = > + <50000000 200000000>, > + <0 0>, > + <0 0>, > + <37500000 150000000>, > + <0 0>, > + <0 0>, > + <0 0>, > + <0 0>; > + > + resets = <&gcc GCC_UFS_BCR>; > + reset-names = "rst"; > + }; > + > + ufsphy: phy@1da7000 { > + compatible = "qcom,sdm845-qmp-ufs-phy"; We should make an 8998 compatible. Also, don't you have phy changes since the init sequence differs between 845 and 8998? > + reg = <0x1da7000 0x18c>; 0x01da7000, see above comment > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + clock-names = "ref", "ref_aux"; > + clocks = > + <&gcc GCC_UFS_CLKREF_CLK>, > + <&gcc GCC_UFS_PHY_AUX_CLK>; > + > + ufsphy_lanes: lanes@1da7400 { > + reg = <0x1da7400 0x128>, > + <0x1da7600 0x1fc>, > + <0x1da7c00 0x1dc>, > + <0x1da7800 0x128>, > + <0x1da7a00 0x1fc>; > + #phy-cells = <0>; > + }; > + }; > }; > }; > >
On 16/01/2019 16:36, Jeffrey Hugo wrote: > On 1/16/2019 3:56 AM, Marc Gonzalez wrote: > >> Add host controller and PHY DT nodes. >> >> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> >> --- >> TODO: check whether the driver uses the 'resets' prop >> --- >> arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 20 +++++++ >> arch/arm64/boot/dts/qcom/msm8998.dtsi | 63 +++++++++++++++++++++++ >> 2 files changed, 83 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi >> index 50e9033aa7f6..cd1c9e84eab7 100644 >> --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi >> +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi >> @@ -257,3 +257,23 @@ >> pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; >> pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; >> }; >> + >> +&ufshc { >> + vdd-hba-fixed-regulator; > > Since we are not specifying the vdd anymore, I suspect this should be > dropped. Do you know of any reason why we'd still need it? Will drop in v3. >> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi >> index 6f4f4b79853b..36fd2e614464 100644 >> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi >> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi >> @@ -711,6 +711,69 @@ >> redistributor-stride = <0x0 0x20000>; >> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> }; >> + >> + ufshc: ufshc@1da4000 { >> + compatible = "qcom,msm8998-ufshc", "qcom,ufshc", >> + "jedec,ufs-2.0"; >> + reg = <0x1da4000 0x2500>; > > Bjorn would like it if reg addresses are full width, ie 0x01da4000 Will tweak in v3. >> + ufsphy: phy@1da7000 { >> + compatible = "qcom,sdm845-qmp-ufs-phy"; > > We should make an 8998 compatible. Also, don't you have phy changes > since the init sequence differs between 845 and 8998? Will create a specific binding. I don't have any PHY changes, I just used the 845 init sequence. I tested this by using the 845 init sequence downstream. However, no point in sending v3 until someone comments on patches 3 and 4 :-) Patch 4 needs to become a real patch. Regards.
diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi index 50e9033aa7f6..cd1c9e84eab7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi @@ -257,3 +257,23 @@ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; }; + +&ufshc { + vdd-hba-fixed-regulator; + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l26a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; +}; + +&ufsphy { + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + vddp-ref-clk-supply = <&vreg_l26a_1p2>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 6f4f4b79853b..36fd2e614464 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -711,6 +711,69 @@ redistributor-stride = <0x0 0x20000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + + ufshc: ufshc@1da4000 { + compatible = "qcom,msm8998-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x1da4000 0x2500>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufsphy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + power-domains = <&gcc UFS_GDSC>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_AXI_CLK>, + <&gcc GCC_AGGRE1_UFS_AXI_CLK>, + <&gcc GCC_UFS_AHB_CLK>, + <&gcc GCC_UFS_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_LN_BB_CLK1>, + <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + resets = <&gcc GCC_UFS_BCR>; + reset-names = "rst"; + }; + + ufsphy: phy@1da7000 { + compatible = "qcom,sdm845-qmp-ufs-phy"; + reg = <0x1da7000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "ref", "ref_aux"; + clocks = + <&gcc GCC_UFS_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_AUX_CLK>; + + ufsphy_lanes: lanes@1da7400 { + reg = <0x1da7400 0x128>, + <0x1da7600 0x1fc>, + <0x1da7c00 0x1dc>, + <0x1da7800 0x128>, + <0x1da7a00 0x1fc>; + #phy-cells = <0>; + }; + }; }; };
Add host controller and PHY DT nodes. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> --- TODO: check whether the driver uses the 'resets' prop --- arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 20 +++++++ arch/arm64/boot/dts/qcom/msm8998.dtsi | 63 +++++++++++++++++++++++ 2 files changed, 83 insertions(+)