From patchwork Mon Feb 7 09:30:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12737109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C230DC433F5 for ; Mon, 7 Feb 2022 09:56:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238718AbiBGJzB (ORCPT ); Mon, 7 Feb 2022 04:55:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352869AbiBGJim (ORCPT ); Mon, 7 Feb 2022 04:38:42 -0500 X-Greylist: delayed 458 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 07 Feb 2022 01:38:40 PST Received: from mx.tkos.co.il (guitar.tcltek.co.il [84.110.109.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F335BC043188; Mon, 7 Feb 2022 01:38:40 -0800 (PST) Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 9C64B440883; Mon, 7 Feb 2022 11:30:37 +0200 (IST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1644226238; bh=LG1R2ibEhTcQ8x9dNJ4eYSWnaeIYekcQQHT0CEdyRZU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gI0ya3JNUqByCXZ+cvm21SUnGCYkfFvaPSmUiazlGd13B1OxQdxdjhUUuG8x84MjL qpTQEWb2uC2wldRSn1FJjfogqxGN+PTeX4kCnQ8PByMjoUDaShJzQX/ysq7SxdCg9F nvEPaDj8naW1uR493Q5CJR0j/L1JOl5Jq+kNx8EXQIA43URdZykPYJiAItYTdxEkEk 6L4VztofVcv1qpNbRqwoq1OOFonbsrChgTHITM6zoSWw21wDgRsmBK7qSxOhV5kU4n Pm5NWNBaPOi8pCfDR73/PkvdXEojOyBrtCR6Tut2gh0ZRS0/rhUXsyJNyqNnfjz+AM ZkEOHF8fRTIRw== From: Baruch Siach To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Andy Gross , Bjorn Andersson Cc: Baruch Siach , Balaji Prakash J , Rob Herring , Robert Marko , Kathiravan T , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] dt-bindings: pwm: add IPQ6018 binding Date: Mon, 7 Feb 2022 11:30:44 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: <17dd231f496d09ed8502bdd505eaa77bb6637e4b.1644226245.git.baruch@tkos.co.il> References: <17dd231f496d09ed8502bdd505eaa77bb6637e4b.1644226245.git.baruch@tkos.co.il> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Baruch Siach DT binding for the PWM block in Qualcomm IPQ6018 SoC. Signed-off-by: Baruch Siach Reviewed-by: Bjorn Andersson --- This series does not convert the TCSR binding documentation to YAML. As a result, this commit adds a new dt_binding_check warning: /example-0/syscon@1937000: failed to match any schema with compatible: ['qcom,tcsr-ipq 6018', 'syscon', 'simple-mfd'] If that is a blocker to IPQ6018 PWM support, so be it. Patches will wait for someone else to push them further. v10: No change v9: Add 'ranges' property to example (Rob) Drop label in example (Rob) v8: Add size cell to 'reg' (Rob) v7: Use 'reg' instead of 'offset' (Rob) Drop 'clock-names' and 'assigned-clock*' (Bjorn) Use single cell address/size in example node (Bjorn) Move '#pwm-cells' lower in example node (Bjorn) List 'reg' as required v6: Device node is child of TCSR; remove phandle (Rob Herring) Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König) v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn Andersson, Kathiravan T) v4: Update the binding example node as well (Rob Herring's bot) v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) v2: Make #pwm-cells const (Rob Herring) --- .../devicetree/bindings/pwm/ipq-pwm.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml new file mode 100644 index 000000000000..857086ad539e --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - Baruch Siach + +properties: + "#pwm-cells": + const: 2 + + compatible: + const: qcom,ipq6018-pwm + + reg: + description: Offset of PWM register in the TCSR block. + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + syscon@1937000 { + compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd"; + reg = <0x01937000 0x21000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1937000 0x21000>; + + pwm: pwm@a010 { + compatible = "qcom,ipq6018-pwm"; + reg = <0xa010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <2>; + }; + };