From patchwork Thu Dec 7 09:21:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Jaiswal X-Patchwork-Id: 13483058 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="l6eEGbLS" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51070A9; Thu, 7 Dec 2023 01:27:12 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B79PDFi021707; Thu, 7 Dec 2023 09:26:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=NxM4Hzj0Zu7rwaDjip3vlG09i1StZxhDtyXhLRHX4Jk=; b=l6eEGbLSPWT5FuNdmyA/B2f4vlsWzBQb1lkbg3e9yWBZtMt5ZHAXo9uQSMsIifxqiI6y CbfDXZ9Xc6eAU0WAAOedp7Ynj2vo6349AzIASEQSmzBRoR6YQWEkLAhHmLI9OKqoxHFe QbTlyLOZxWn9EBQXjPiwYvNBsn4V1XnDD45M7CIfB0BFL5c29XFkiTm+LVGC7SYawtjh QsQ+QcgsQK+GJOAlBAXmJBG/XKHlCQ3eFqi8MDYXTAv85Ona26I74e60Sk2Azf85psgj vzVmrLUfPOK27JHemy2o+4f6wSvmVjpNNosHfpQiV34g+do+dP78GR/AfInHnxBa7sBg iQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uubd8003y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Dec 2023 09:26:59 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3B79QwsS010240 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Dec 2023 09:26:58 GMT Received: from hu-jsuraj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 7 Dec 2023 01:26:48 -0800 From: Suraj Jaiswal To: , Vinod Koul , Bhupesh Sharma , Andy Gross , Bjorn Andersson , Konrad Dybcio , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Alexandre Torgue , "Jose Abreu" , Maxime Coquelin , , , , , , Prasad Sodagudi , Andrew Halaney CC: Subject: [PATCH net-next v4 2/3] arm64: dts: qcom: sa8775p: enable safety IRQ Date: Thu, 7 Dec 2023 14:51:26 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SdEEumA_yh7g-Liz5R15c4C3chM29-iN X-Proofpoint-ORIG-GUID: SdEEumA_yh7g-Liz5R15c4C3chM29-iN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-07_06,2023-12-06_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 suspectscore=0 mlxlogscore=657 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 mlxscore=0 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2312070076 Add changes to support safety IRQ handling support for ethernet. Signed-off-by: Suraj Jaiswal --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 6b92f9083104..a3ed75a1314c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2394,8 +2394,9 @@ ethernet1: ethernet@23000000 { <0x0 0x23016000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "safety"; clocks = <&gcc GCC_EMAC1_AXI_CLK>, <&gcc GCC_EMAC1_SLV_AHB_CLK>, @@ -2427,8 +2428,9 @@ ethernet0: ethernet@23040000 { <0x0 0x23056000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "safety"; clocks = <&gcc GCC_EMAC0_AXI_CLK>, <&gcc GCC_EMAC0_SLV_AHB_CLK>,