From patchwork Fri Dec 28 08:09:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erin Lo X-Patchwork-Id: 10744217 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45DE56C5 for ; Fri, 28 Dec 2018 08:10:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C90328BE3 for ; Fri, 28 Dec 2018 08:10:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1BFA328BE6; Fri, 28 Dec 2018 08:10:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9CFAD28BE3 for ; Fri, 28 Dec 2018 08:10:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727989AbeL1IKA (ORCPT ); Fri, 28 Dec 2018 03:10:00 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:7077 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728006AbeL1IKA (ORCPT ); Fri, 28 Dec 2018 03:10:00 -0500 X-UUID: c2721f1436b0405aa4f384da51032f57-20181228 X-UUID: c2721f1436b0405aa4f384da51032f57-20181228 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1889686763; Fri, 28 Dec 2018 16:09:53 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 28 Dec 2018 16:09:50 +0800 Received: from mtkslt303.mediatek.inc (10.21.14.116) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 28 Dec 2018 16:09:50 +0800 From: Erin Lo To: Matthias Brugger , Rob Herring , Mark Rutland , Thomas Gleixner , Jason Cooper , Marc Zyngier , Greg Kroah-Hartman , Stephen Boyd CC: , srv_heupstream , , , , , , , , , Subject: [PATCH v5 0/6] Add basic and clock support for Mediatek MT8183 SoC Date: Fri, 28 Dec 2018 16:09:35 +0800 Message-ID: <1545984581-25843-1-git-send-email-erin.lo@mediatek.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-TM-SNTS-SMTP: 03A174E426CB1C589FDC2791DACB0D395FA53E3951E9A9D31D983E2BDC60B6512000:8 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MT8183 is a SoC based on 64bit ARMv8 architecture. It contains 4 CA53 and 4 CA73 cores. MT8183 share many HW IP with MT65xx series. This patchset was tested on MT8183 evaluation board and use correct clock to shell. This series contains document bindings, device tree including interrupt, uart, clock, pinctrl, power, iommu, spi, and pwrap. Based on v4.20-rc1 and http://lists.infradead.org/pipermail/linux-mediatek/2018-December/016243.html http://lists.infradead.org/pipermail/linux-mediatek/2018-December/016205.html http://lists.infradead.org/pipermail/linux-mediatek/2018-October/015676.html Change in v5: 1. Collect all device tree nodes to the last patch 2. Add PMU 3. Add Signed-off-by 4. Remove clock driver code and binding doc 5. Add pinctrl, iommu, spi, and pwrap nodes Change in v4: 1. Correct syntax error in dtsi 2. Add MT8183 clock support Change in v3: 1. Fill out GICC, GICH, GICV regions 2. Update Copyright to 2018 Change in v2: 1. Split dt-bindings into different patches 2. Correct bindings for supported SoCs (mtk-uart.txt) Ben Ho (1): arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile Erin Lo (3): dt-bindings: arm: Add bindings for Mediatek MT8183 SoC Platform dt-bindings: mtk-sysirq: Add compatible for Mediatek MT8183 dt-bindings: serial: Add compatible for Mediatek MT8183 Seiya Wang (1): irqchip/mtk-sysirq: support 4 interrupt parameters for sysirq Zhiyong Tao (1): dt-bindings: pinctrl: mt8183: add binding document Documentation/devicetree/bindings/arm/mediatek.txt | 4 + .../interrupt-controller/mediatek,sysirq.txt | 1 + .../devicetree/bindings/pinctrl/pinctrl-mt8183.txt | 110 ++ .../devicetree/bindings/serial/mtk-uart.txt | 1 + arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 136 +++ arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h | 1120 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 547 ++++++++++ drivers/irqchip/irq-mtk-sysirq.c | 4 +- 9 files changed, 1922 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi --- 1.9.1