From patchwork Fri Feb 21 09:52:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 11395967 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 861DD138D for ; Fri, 21 Feb 2020 09:52:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5C70B222C4 for ; Fri, 21 Feb 2020 09:52:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MDZToudB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728375AbgBUJwf (ORCPT ); Fri, 21 Feb 2020 04:52:35 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:23893 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726989AbgBUJwf (ORCPT ); Fri, 21 Feb 2020 04:52:35 -0500 X-UUID: 2e534da1a58c42bda6f01e4e9cc0387f-20200221 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=d/WFlzDa3S2eOt2IkKMzp95187HzPikccPGAx6OY+ks=; b=MDZToudBH8ip+Ztx5jNMegXDvOZNGAMvN2YSA9j7SdkhRJA9toKJyYU091jbnDz6+3yP6cNlVwJtPsKicJWXzb4O55PPaVCnZtN/ztpJCfVf0DdMR7N4kNm545HiUcexjsajfF1U1lCZ4mfdvBpW1SHGkBnZjqGIvymKT/7rNto=; X-UUID: 2e534da1a58c42bda6f01e4e9cc0387f-20200221 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 946751563; Fri, 21 Feb 2020 17:52:31 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 21 Feb 2020 17:51:43 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 21 Feb 2020 17:52:59 +0800 From: Macpaul Lin To: Rob Herring , Mark Rutland , Matthias Brugger , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , mtk01761 , Fabien Parent , Weiyi Lu , Mars Cheng , Sean Wang , Macpaul Lin , Owen Chen , Chunfeng Yun , Evan Green , Yong Wu , Joerg Roedel , Shawn Guo , Marc Zyngier , Ryder Lee , , , , , CC: Mediatek WSD Upstream , CC Hwang , Loda Chou Subject: [PATCH 0/5] Add basic clock support for mt6765 Date: Fri, 21 Feb 2020 17:52:17 +0800 Message-ID: <1582278742-1626-1-git-send-email-macpaul.lin@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch set adds basic clock support for Mediatek's new 8-core SoC, MT6765, which is mainly for smartphone application. Which has been split from previous patch set v7: Add basic SoC support for mt6765. https://patchwork.kernel.org/cover/11370105/ Changes in this patch set: 1. Take patches #1, #3, #4 from origin patch set. - [v7,1/7] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC - [v7,3/7] clk: mediatek: add mt6765 clock IDs - [v7,4/7] clk: mediatek: Add MT6765 clock support 2. Split origin patch #1 into 3 patches: - [PATCH 1/5] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC - [PATCH 2/5] dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC - [PATCH 3/5] dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC Macpaul Lin (3): dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC Mars Cheng (1): clk: mediatek: add mt6765 clock IDs Owen Chen (1): clk: mediatek: Add MT6765 clock support .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,camsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mipi0a.txt | 28 + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../arm/mediatek/mediatek,pericfg.txt | 1 + .../arm/mediatek/mediatek,topckgen.txt | 1 + .../arm/mediatek/mediatek,vcodecsys.txt | 27 + drivers/clk/mediatek/Kconfig | 86 ++ drivers/clk/mediatek/Makefile | 7 + drivers/clk/mediatek/clk-mt6765-audio.c | 100 ++ drivers/clk/mediatek/clk-mt6765-cam.c | 74 ++ drivers/clk/mediatek/clk-mt6765-img.c | 70 ++ drivers/clk/mediatek/clk-mt6765-mipi0a.c | 68 ++ drivers/clk/mediatek/clk-mt6765-mm.c | 96 ++ drivers/clk/mediatek/clk-mt6765-vcodec.c | 70 ++ drivers/clk/mediatek/clk-mt6765.c | 952 ++++++++++++++++++ include/dt-bindings/clock/mt6765-clk.h | 313 ++++++ 20 files changed, 1899 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt create mode 100644 drivers/clk/mediatek/clk-mt6765-audio.c create mode 100644 drivers/clk/mediatek/clk-mt6765-cam.c create mode 100644 drivers/clk/mediatek/clk-mt6765-img.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mipi0a.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mm.c create mode 100644 drivers/clk/mediatek/clk-mt6765-vcodec.c create mode 100644 drivers/clk/mediatek/clk-mt6765.c create mode 100644 include/dt-bindings/clock/mt6765-clk.h