From patchwork Thu Oct 22 12:55:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11851183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 541DCC388F7 for ; Thu, 22 Oct 2020 12:57:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED046223BF for ; Thu, 22 Oct 2020 12:57:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="WR2E9cNT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2899033AbgJVM4M (ORCPT ); Thu, 22 Oct 2020 08:56:12 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:44046 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2899026AbgJVM4M (ORCPT ); Thu, 22 Oct 2020 08:56:12 -0400 X-UUID: ada377b4dd8645d09b260f125417036b-20201022 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=ovUUUcqhJC9H5EtfgPHi7yKW/d7yDwoYEfaWYv3LJUw=; b=WR2E9cNT7cQN5gj340ED1PUpcM6E3aS7Gf4+nIcD9rswevQTix1dr1lbHRlmt6/wm9zHo5lmVK50hHmm2hqkvSpT87QUqtxB+OpdgCHgiLhbYjVVSqC6ojd+lz268POzjiRnuxsgqAZ5RXrIusZDG1JMkAKXfsiz36DJNvNRsvM=; X-UUID: ada377b4dd8645d09b260f125417036b-20201022 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 997616852; Thu, 22 Oct 2020 20:56:08 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Oct 2020 20:56:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Oct 2020 20:56:06 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Nicolas Boichat CC: , , , , , Weiyi Lu Subject: [PATCH 00/12] Clean up the pll_en_bit from en_mask on all the MediaTek clock drivers Date: Thu, 22 Oct 2020 20:55:53 +0800 Message-ID: <1603371365-30863-1-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This series is based on v5.9-rc1 and [v4,09/34] clk: mediatek: Fix asymmetrical PLL enable and disable control[1] in Mediatek MT8192 clock support series [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1603370247-30437-10-git-send-email-weiyi.lu@mediatek.com/ Weiyi Lu (12): clk: mediatek: Clean up the pll_en_bit from en_mask on MT2701 clk: mediatek: Clean up the pll_en_bit from en_mask on MT2712 clk: mediatek: Clean up the pll_en_bit from en_mask on MT6765 clk: mediatek: Clean up the pll_en_bit from en_mask on MT6779 clk: mediatek: Clean up the pll_en_bit from en_mask on MT6797 clk: mediatek: Clean up the pll_en_bit from en_mask on MT7622 clk: mediatek: Clean up the pll_en_bit from en_mask on MT7629 clk: mediatek: Clean up the pll_en_bit from en_mask on MT8135 clk: mediatek: Clean up the pll_en_bit from en_mask on MT8173 clk: mediatek: Clean up the pll_en_bit from en_mask on MT8183 clk: mediatek: Clean up the pll_en_bit from en_mask on MT8516 clk: mediatek: limit en_mask to a pure div_en_mask drivers/clk/mediatek/clk-mt2701.c | 26 +++++++++++++------------- drivers/clk/mediatek/clk-mt2712.c | 30 +++++++++++++++--------------- drivers/clk/mediatek/clk-mt6765.c | 20 ++++++++++---------- drivers/clk/mediatek/clk-mt6779.c | 24 ++++++++++++------------ drivers/clk/mediatek/clk-mt6797.c | 20 ++++++++++---------- drivers/clk/mediatek/clk-mt7622.c | 18 +++++++++--------- drivers/clk/mediatek/clk-mt7629.c | 12 ++++++------ drivers/clk/mediatek/clk-mt8135.c | 20 ++++++++++---------- drivers/clk/mediatek/clk-mt8173.c | 28 ++++++++++++++-------------- drivers/clk/mediatek/clk-mt8183.c | 22 +++++++++++----------- drivers/clk/mediatek/clk-mt8516.c | 12 ++++++------ drivers/clk/mediatek/clk-pll.c | 12 ++++-------- 12 files changed, 120 insertions(+), 124 deletions(-)