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Wed, 18 Nov 2020 08:38:33 +0000 From: Liu Ying To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, robh+dt@kernel.org, aisheng.dong@nxp.com Subject: [PATCH 0/5] Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems Date: Wed, 18 Nov 2020 16:31:25 +0800 Message-Id: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3589.17 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: J9vyj7Cez8wHqeMDQyr7q/bNwVaS1oZiKALmbz/sdLZhc+QS5VD9DrsXnGudxDuDNWu4DVGEjeEFnun9TO20Mw8FNyM8ZAfcnXUvZbvt+rh7Z/5eW2kStRGKHrznYCte9Apn7DqEkaIlmUz7P15iS+x745x5HwJvpIFw6mfRZ3KrdEKApLbSDPi0iPm1tN+e+8OS277G0tq1ac+PXiEXHP8qwOXySmyCk1Q242bYHhmvbiosR+/XqSPLGVtbRDrjlBzVRFEz47arrdrxU9FGSiLzQA0fk/ZyapfLXFNRbvJczTmwYDuL6DTdvvVwSjbBeQpgQcLr4Z0Tl9GF7gQE3Ado4pLVuCWnaIZJmMunJqKMZA+wE3X6TLEw5tpRlBYXHG7kC/7sB9rAoQSpj0ChBoD3r50I/Yh0vp+Q0a4d5dTD3hqtClpube4qTuI+arCB2ttIJQy4fRaWRDvuKIVVEjW4RRRH/ukvGvl9HBYzw5EyutzV0acQhxkGeWYYfEEpImB4auRFFO5Xnpg6daVmI8q/jKb5rpNJWlq10B5hOEwi3rB3KyTi9KZc+elr/PnARJmn4zHRzF9Rrf755WarOEq1RJDq6VeldqK8g5FpnpWT73uLQaAJEJGnypBraDNo/f3Li6QcD4JH5lwE671qEA== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3dd31205-116b-45c0-e336-08d88b9d557a X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2020 08:38:33.5477 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kPPmorw8tthZ+yeQpaF8KBIAPlrjMLfxg5yo1Ah6l+AQN1xJv4MNVYZgZpZe852hcr/NXxV/4flPwBR5fA1L3w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6990 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch set adds some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems, which includes some SCU controlled clocks and some LPCG clocks. With this patch set, some basic clocks for i.MX8qxp LVDS displays can be got by drivers. This patch set follows the legacy/deprecated way to add the clocks support in clock drivers instead of the new 'two cells' dt-binding way. The reason behind this is that the existing i.MX8qxp SoC device tree is using the legacy way(no conversion effort is seen) and there is not i.MX8qm(with a similar architecture) SoC device tree for us to enable display yet. Liu Ying (5): clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks clk: imx: clk-imx8qxp-lpcg: Add display controller LPCG clocks support clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems dt-bindings: clock: imx8qxp-lpcg: Add compatibles for MIPI-LVDS subsystems clk: imx: clk-imx8qxp-lpcg: Add some LPCG clocks support for MIPI-LVDS subsystems .../devicetree/bindings/clock/imx8qxp-lpcg.yaml | 2 + drivers/clk/imx/clk-imx8qxp-lpcg.c | 79 ++++++++++++++++++++++ drivers/clk/imx/clk-imx8qxp-lpcg.h | 29 ++++++++ drivers/clk/imx/clk-imx8qxp.c | 12 ++++ include/dt-bindings/clock/imx8-clock.h | 61 +++++++++++++++++ 5 files changed, 183 insertions(+)