From patchwork Tue Dec 22 13:40:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11986661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F1C2C433E0 for ; Tue, 22 Dec 2020 13:41:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD72F23105 for ; Tue, 22 Dec 2020 13:41:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727243AbgLVNlD (ORCPT ); Tue, 22 Dec 2020 08:41:03 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:52566 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727139AbgLVNlD (ORCPT ); Tue, 22 Dec 2020 08:41:03 -0500 X-UUID: 771dcc73bfb44340af25703dfec2d671-20201222 X-UUID: 771dcc73bfb44340af25703dfec2d671-20201222 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 198406221; Tue, 22 Dec 2020 21:40:16 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Dec 2020 21:40:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 22 Dec 2020 21:40:12 +0800 From: Weiyi Lu To: Matthias Brugger , Rob Herring , Nicolas Boichat CC: , , , , , , , Weiyi Lu Subject: [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes Date: Tue, 22 Dec 2020 21:40:12 +0800 Message-ID: <1608644414-17793-1-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This series is based on v5.10-rc1, MT8192 dts v6[1] and MT8192 clock v6 series[2]. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=373899 [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=405295 Weiyi Lu (2): arm64: dts: mediatek: Add mt8192 clock controllers arm64: dts: mediatek: Correct UART0 bus clock of MT8192 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 165 ++++++++++++++++++++++- 1 file changed, 164 insertions(+), 1 deletion(-)