From patchwork Sun Aug 28 19:21:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12957296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6FF0ECAAD5 for ; Sun, 28 Aug 2022 19:22:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229543AbiH1TWN (ORCPT ); Sun, 28 Aug 2022 15:22:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229977AbiH1TWK (ORCPT ); Sun, 28 Aug 2022 15:22:10 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E431B248EE; Sun, 28 Aug 2022 12:22:06 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27SJKtPn008995; Sun, 28 Aug 2022 19:21:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=sDjRq8TtTtOhhdLNcU6fwDRQqh6Cf4gWnhHDwyUoa78=; b=bg3Lrxj5COkokA0UNDOef+YLeepRPt/QwPZ2GIWO9WKQJxHdi8RzoDsDeZbYCw7ToMSr 9a6vW/K6f+pxhZHgCF+Mqb/oB+1N4yMP3kXHIQ8v2Q4A6GyNiYzBVeI0KUCImEUllTrg QN1rEerD+LH89WCLt8U5jXJk1wK5kndNPLtkHEaz1Bw5x3PQvosuFCluQ9wxs3kpVwDY Big6BmzYwLTADdAnXjY8EMOTaTqmwzUsCkfp9RX3exMPE1thy2s3ijeII03cfAuwWlEC 2xgdUr76SehKwfg1w+YCLY9NqsWIp2HM3EOA1QScalUK8VYrtJfi0HED7kpwzdKwgxf2 og== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3j7cjf2m84-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 28 Aug 2022 19:21:46 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27SJLjtt031198 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 28 Aug 2022 19:21:45 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Sun, 28 Aug 2022 12:21:38 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" , Dmitry Baryshkov CC: , Douglas Anderson , Akhil P Oommen , "Abhinav Kumar" , Andy Gross , "Daniel Vetter" , David Airlie , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Rob Herring , Sean Paul , Stephen Boyd , , , Subject: [PATCH v5 0/6] clk/qcom: Support gdsc collapse polling using 'reset' interface Date: Mon, 29 Aug 2022 00:51:13 +0530 Message-ID: <1661714479-28981-1-git-send-email-quic_akhilpo@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mc4o8glu7q703h3L4d1-ddhZaMgHzsFL X-Proofpoint-ORIG-GUID: mc4o8glu7q703h3L4d1-ddhZaMgHzsFL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-28_12,2022-08-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 phishscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208280080 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Some clients like adreno gpu driver would like to ensure that its gdsc is collapsed at hardware during a gpu reset sequence. This is because it has a votable gdsc which could be ON due to a vote from another subsystem like tz, hyp etc or due to an internal hardware signal. To allow this, gpucc driver can expose an interface to the client driver using reset framework. Using this the client driver can trigger a polling within the gdsc driver. This series is rebased on top of linus's master branch. Related discussion: https://patchwork.freedesktop.org/patch/493144/ Changes in v5: - Nit: Remove a duplicate blank line (Krzysztof) Changes in v4: - Update gpu dt-binding schema - Typo fix in commit text Changes in v3: - Use pointer to const for "struct qcom_reset_ops" in qcom_reset_map (Krzysztof) Changes in v2: - Return error when a particular custom reset op is not implemented. (Dmitry) Akhil P Oommen (6): dt-bindings: clk: qcom: Support gpu cx gdsc reset clk: qcom: Allow custom reset ops clk: qcom: gdsc: Add a reset op to poll gdsc collapse clk: qcom: gpucc-sc7280: Add cx collapse reset support dt-bindings: drm/msm/gpu: Add optional resets arm64: dts: qcom: sc7280: Add Reset support for gpu .../devicetree/bindings/display/msm/gpu.yaml | 6 +++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ drivers/clk/qcom/gdsc.c | 23 ++++++++++++++---- drivers/clk/qcom/gdsc.h | 7 ++++++ drivers/clk/qcom/gpucc-sc7280.c | 10 ++++++++ drivers/clk/qcom/reset.c | 27 ++++++++++++++++++++++ drivers/clk/qcom/reset.h | 8 +++++++ include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ 8 files changed, 83 insertions(+), 4 deletions(-)