| Message ID | 20181129105008.10239-1-geert+renesas@glider.be (mailing list archive) |
|---|---|
| Headers | show |
| Series | clk: renesas: Miscellaneous fixes | expand |
Hi Geert, On Thursday, 29 November 2018 12:49:55 EET Geert Uytterhoeven wrote: > Hi Mike, Stephen, Laurent, Kieran, > > This patch series contains several fixes for the Renesas Clock drivers > and DT bindings, and a small simplification: > - Removal of non-existent clocks, > - Addition of the CPEX clocks, which can be used a source for a timer > (CMT1), > - Correction of DU parent clocks. > Most of these have been found by skimming the Hardware Manual Errata. > > This has been boot-tested on Salvator-X(S) (R-Car H3, M3-W, M3-N), Eagle > (R-Car V3M), and Draak (R-Car D3), except for the DU parts. > Testing of the DU on R-Car D3 and E3 would be appreciated, as the DU > driver may have a workaround for the incorrect parent clock rates. As explained in my review of 09/13, I believe the DU clock patches to both be correct and have no effect for D3 and E3. No action is needed on the DU side, there is no workaround for the incorrect frequency. > I intend to queue this in clk-renesas-for-v4.21. > > Thanks! > > Geert Uytterhoeven (12): > dt-bindings: clock: r8a7795: Remove CSIREF clock > dt-bindings: clock: r8a7796: Remove CSIREF clock > clk: renesas: r8a774a1: Add CPEX clock > clk: renesas: r8a7795: Add CPEX clock > clk: renesas: r8a7796: Add CPEX clock > clk: renesas: r8a77965: Add CPEX clock > clk: renesas: r8a77970: Add CPEX clock > clk: renesas: r8a77995: Correct parent clock of DU > clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks > clk: renesas: r8a77995: Remove non-existent SSP clocks > clk: renesas: r8a77995: Add missing CPEX clock > clk: renesas: r8a77995: Simplify PLL3 multiplier/divider > > Takeshi Kihara (1): > clk: renesas: r8a77990: Correct parent clock of DU > > drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 + > drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 + > drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + > drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 + > drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 + > drivers/clk/renesas/r8a77990-cpg-mssr.c | 4 ++-- > drivers/clk/renesas/r8a77995-cpg-mssr.c | 15 ++++++--------- > include/dt-bindings/clock/r8a7795-cpg-mssr.h | 2 +- > include/dt-bindings/clock/r8a7796-cpg-mssr.h | 2 +- > include/dt-bindings/clock/r8a77995-cpg-mssr.h | 5 +++-- > 10 files changed, 18 insertions(+), 15 deletions(-)
Quoting Geert Uytterhoeven (2018-11-29 02:49:55) > Hi Mike, Stephen, Laurent, Kieran, > > This patch series contains several fixes for the Renesas Clock drivers > and DT bindings, and a small simplification: > - Removal of non-existent clocks, > - Addition of the CPEX clocks, which can be used a source for a timer > (CMT1), > - Correction of DU parent clocks. > Most of these have been found by skimming the Hardware Manual Errata. > > This has been boot-tested on Salvator-X(S) (R-Car H3, M3-W, M3-N), Eagle > (R-Car V3M), and Draak (R-Car D3), except for the DU parts. > Testing of the DU on R-Car D3 and E3 would be appreciated, as the DU > driver may have a workaround for the incorrect parent clock rates. > > I intend to queue this in clk-renesas-for-v4.21. > Ok. For the whole series: Acked-by: Stephen Boyd <sboyd@kernel.org>
Hi Mike, Stephen, Laurent, Kieran, This patch series contains several fixes for the Renesas Clock drivers and DT bindings, and a small simplification: - Removal of non-existent clocks, - Addition of the CPEX clocks, which can be used a source for a timer (CMT1), - Correction of DU parent clocks. Most of these have been found by skimming the Hardware Manual Errata. This has been boot-tested on Salvator-X(S) (R-Car H3, M3-W, M3-N), Eagle (R-Car V3M), and Draak (R-Car D3), except for the DU parts. Testing of the DU on R-Car D3 and E3 would be appreciated, as the DU driver may have a workaround for the incorrect parent clock rates. I intend to queue this in clk-renesas-for-v4.21. Thanks! Geert Uytterhoeven (12): dt-bindings: clock: r8a7795: Remove CSIREF clock dt-bindings: clock: r8a7796: Remove CSIREF clock clk: renesas: r8a774a1: Add CPEX clock clk: renesas: r8a7795: Add CPEX clock clk: renesas: r8a7796: Add CPEX clock clk: renesas: r8a77965: Add CPEX clock clk: renesas: r8a77970: Add CPEX clock clk: renesas: r8a77995: Correct parent clock of DU clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks clk: renesas: r8a77995: Remove non-existent SSP clocks clk: renesas: r8a77995: Add missing CPEX clock clk: renesas: r8a77995: Simplify PLL3 multiplier/divider Takeshi Kihara (1): clk: renesas: r8a77990: Correct parent clock of DU drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77990-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a77995-cpg-mssr.c | 15 ++++++--------- include/dt-bindings/clock/r8a7795-cpg-mssr.h | 2 +- include/dt-bindings/clock/r8a7796-cpg-mssr.h | 2 +- include/dt-bindings/clock/r8a77995-cpg-mssr.h | 5 +++-- 10 files changed, 18 insertions(+), 15 deletions(-)