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[2003:f1:371c:b100:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id n23sm16632977wmc.18.2019.11.17.06.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2019 06:07:39 -0800 (PST) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, Martin Blumenstingl Subject: [PATCH v3 0/2] add the DDR clock controller on Meson8 and Meson8b Date: Sun, 17 Nov 2019 15:07:29 +0100 Message-Id: <20191117140731.137378-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Meson8 and Meson8b SoCs embed a DDR clock controller in their MMCBUS registers. This series: - adds support for this DDR clock controller (patches 0 and 1) - wires up the DDR PLL as input for two audio clocks (patches 2 and 3) - adds the DDR clock controller to meson8.dtsi and meson8b.dtsi Special thanks go out to Alexandre Mergnat for switching the Amlogic clock drivers over to parent_hws and parent_data. That made this series a lot easier for me! This series depends on v3 my other series from [0]: "provide the XTAL clock via OF on Meson8/8b/8m2" Changes since v2 at [2]: - add #include as suggested by Stephen Boyd - drop unused includes - use devm_platform_ioremap_resource instead of open-coding it as suggested by Stephen Boyd - drop trailing comma after sentinel element as suggested by Stephen Boyd - dropped patch #3 "clk: meson: meson8b: use of_clk_hw_register to register the clocks" because it's now moved to my other series at [0] - dropped dts changes so this series exclusively targets clk-meson Changes since v1 at [1]: - fixed the license of the .yaml binding and added Rob's Reviewed-by - drop unused syscon.h include (spotted by Jerome - thanks) - drop fast_io from regmap_config and add max_register as suggested by Jerome - dropped original patch #4 "clk: meson: meson8b: add the ddr_pll input for the audio clocks" because I could not test that yet (that patch was a forward-port from Amlogic's 3.10 BSP kernel) [0] https://patchwork.kernel.org/cover/11248377/ [1] https://patchwork.kernel.org/cover/11155553/ [2] https://patchwork.kernel.org/cover/11214227/ Martin Blumenstingl (2): dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller .../clock/amlogic,meson8-ddr-clkc.yaml | 50 ++++++ drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/meson8-ddr.c | 149 ++++++++++++++++++ include/dt-bindings/clock/meson8-ddr-clkc.h | 4 + 4 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml create mode 100644 drivers/clk/meson/meson8-ddr.c create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h