[v2,00/15] soc: xilinx: vcu: Convert driver to clock provider

Message

Michael Tretter Dec. 21, 2020, 3:06 p.m. UTC

Hello,

the xlnx_vcu soc driver is actually a clock provider of a PLL and four output
clocks created from the PLL via dividers.

This is v2 of the series to transform the driver into a proper clock provider
driver.

The main changes compared to v1 are:

Get rid of the "dummy" clock and remove the manual switching of the mux in the
output clocks. The driver now uses the pll_ref as a bypass clock. As this is
not documented, I am not sure if this is actually the case, but without
another signal for an external clock to the ip core, this seems plausible and
avoids changes to the device tree binding. The reparenting happens
automatically when setting a rate on the output clocks.

Add a few patches to cleanup checkpatch warnings on the driver itself.

Move the entire driver from drivers/soc to drivers/clk, because the driver is
now actually only clock provider driver.

A more detailed changelog is attached to the respective patches.

The series is based on the zynqmp/soc-next branch in the Xilinx downstream
repository [0] which should be merged to mainline soon.

Michael

[0] https://github.com/Xilinx/linux-xlnx/tree/zynqmp/soc-next

Changelog:

v2:
- Remove dummy clock and explicit re-parenting of mux clocks
- Add patches to fix checkpatch warnings
- Move driver from drivers/soc to drivers/clk
- Use clk_parent_data instead of parent_names
- Add missing decoder clocks
- Fix smatch warnings
- Fix kernel-doc

Michael Tretter (15):
  ARM: dts: vcu: define indexes for output clocks
  clk: divider: fix initialization with parent_hw
  soc: xilinx: vcu: drop coreclk from struct xlnx_vcu
  soc: xilinx: vcu: add helper to wait for PLL locked
  soc: xilinx: vcu: add helpers for configuring PLL
  soc: xilinx: vcu: implement PLL disable
  soc: xilinx: vcu: register PLL as fixed rate clock
  soc: xilinx: vcu: implement clock provider for output clocks
  soc: xilinx: vcu: make pll post divider explicit
  soc: xilinx: vcu: make the PLL configurable
  soc: xilinx: vcu: remove calculation of PLL configuration
  soc: xilinx: vcu: use bitfields for register definition
  soc: xilinx: vcu: fix repeated word the in comment
  soc: xilinx: vcu: fix alignment to open parenthesis
  clk: xilinx: move xlnx_vcu clock driver from soc

 drivers/clk/Kconfig                  |   1 +
 drivers/clk/Makefile                 |   1 +
 drivers/clk/clk-divider.c            |   9 +-
 drivers/clk/xilinx/Kconfig           |  19 +
 drivers/clk/xilinx/Makefile          |   2 +
 drivers/clk/xilinx/xlnx_vcu.c        | 742 +++++++++++++++++++++++++++
 drivers/soc/xilinx/Kconfig           |  17 -
 drivers/soc/xilinx/Makefile          |   1 -
 drivers/soc/xilinx/xlnx_vcu.c        | 628 -----------------------
 include/dt-bindings/clock/xlnx-vcu.h |  15 +
 10 files changed, 787 insertions(+), 648 deletions(-)
 create mode 100644 drivers/clk/xilinx/Kconfig
 create mode 100644 drivers/clk/xilinx/Makefile
 create mode 100644 drivers/clk/xilinx/xlnx_vcu.c
 delete mode 100644 drivers/soc/xilinx/xlnx_vcu.c
 create mode 100644 include/dt-bindings/clock/xlnx-vcu.h

Comments

Michal Simek Jan. 7, 2021, 10:10 a.m. UTC | #1

Hi,

On 21. 12. 20 16:06, Michael Tretter wrote:
> Hello,
> 
> the xlnx_vcu soc driver is actually a clock provider of a PLL and four output
> clocks created from the PLL via dividers.
> 
> This is v2 of the series to transform the driver into a proper clock provider
> driver.
> 
> The main changes compared to v1 are:
> 
> Get rid of the "dummy" clock and remove the manual switching of the mux in the
> output clocks. The driver now uses the pll_ref as a bypass clock. As this is
> not documented, I am not sure if this is actually the case, but without
> another signal for an external clock to the ip core, this seems plausible and
> avoids changes to the device tree binding. The reparenting happens
> automatically when setting a rate on the output clocks.
> 
> Add a few patches to cleanup checkpatch warnings on the driver itself.
> 
> Move the entire driver from drivers/soc to drivers/clk, because the driver is
> now actually only clock provider driver.
> 
> A more detailed changelog is attached to the respective patches.
> 
> The series is based on the zynqmp/soc-next branch in the Xilinx downstream
> repository [0] which should be merged to mainline soon.
> 
> Michael
> 
> [0] https://github.com/Xilinx/linux-xlnx/tree/zynqmp/soc-next

Series looks good to me but not clock expert.

Stephen: Please let me know if you want me to take it via my tree.
If yes please ack that 15/15.

For the whole series please add
Acked-by: Michal Simek <[e-mail]>
when that minor kerneldoc issue in 9/15 is fixed.

Thanks,
Michal