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[109.252.193.52]) by smtp.gmail.com with ESMTPSA id t17sm957024lft.224.2021.03.20.08.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Mar 2021 08:28:08 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 0/7] Couple improvements for Tegra clk driver Date: Sat, 20 Mar 2021 18:26:41 +0300 Message-Id: <20210320152648.8389-1-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This series fixes couple minor standalone problems of the Tegra clk driver. Changelog: v6: - Made a small improvement and corrected a typo in patch "Fix refcounting of gate clocks" that were spotted by Michał Mirosław. v5: - Corrected example in the schema binding to silence dt_binding_check warning. - The Tegra124 binding is factored out into standalone binding since Tegra124 has properties that aren't used by other SoCs and I couldn't figure out how to make them conditional in schema. v4: - Added new patch that converts DT bindings to schema. v3: - Added acks from Thierry Reding that he gave to v2. - Added new patch "clk: tegra: Don't allow zero clock rate for PLLs". v2: - Added these new patches: clk: tegra: Halve SCLK rate on Tegra20 MAINTAINERS: Hand Tegra clk driver to Jon and Thierry v1: - Collected clk patches into a single series. Dmitry Osipenko (7): clk: tegra30: Use 300MHz for video decoder by default clk: tegra: Fix refcounting of gate clocks clk: tegra: Ensure that PLLU configuration is applied properly clk: tegra: Halve SCLK rate on Tegra20 MAINTAINERS: Hand Tegra clk driver to Jon and Thierry clk: tegra: Don't allow zero clock rate for PLLs dt-bindings: clock: tegra: Convert to schema CREDITS | 6 + .../bindings/clock/nvidia,tegra114-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra124-car.txt | 107 ---------------- .../bindings/clock/nvidia,tegra124-car.yaml | 115 ++++++++++++++++++ .../bindings/clock/nvidia,tegra20-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra20-car.yaml | 69 +++++++++++ .../bindings/clock/nvidia,tegra210-car.txt | 56 --------- .../bindings/clock/nvidia,tegra30-car.txt | 63 ---------- MAINTAINERS | 4 +- drivers/clk/tegra/clk-periph-gate.c | 72 +++++++---- drivers/clk/tegra/clk-periph.c | 11 ++ drivers/clk/tegra/clk-pll.c | 12 +- drivers/clk/tegra/clk-tegra20.c | 6 +- drivers/clk/tegra/clk-tegra30.c | 2 +- 14 files changed, 261 insertions(+), 388 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt