From patchwork Wed Aug 4 18:08:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12419551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51C22C4338F for ; Wed, 4 Aug 2021 18:08:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 37F4B60C3E for ; Wed, 4 Aug 2021 18:08:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238576AbhHDSIY (ORCPT ); Wed, 4 Aug 2021 14:08:24 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:43174 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S238289AbhHDSIY (ORCPT ); Wed, 4 Aug 2021 14:08:24 -0400 X-IronPort-AV: E=Sophos;i="5.84,295,1620658800"; d="scan'208";a="89818616" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 05 Aug 2021 03:08:09 +0900 Received: from localhost.localdomain (unknown [10.226.92.21]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9E69F40BF1F2; Thu, 5 Aug 2021 03:08:07 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , Wolfram Sang , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 0/2] Add SDHI clock and reset entries in cpg driver Date: Wed, 4 Aug 2021 19:08:01 +0100 Message-Id: <20210804180803.29087-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add SDHI clock and reset entries in cpg driver. As per the HW manual, we should not directly switch from 533 MHz to 400 MHz and vice versa. To change the setting from 533 MHz to 400 MHz or vice versa, Switch to 266 MHz first,and then switch to the target setting 533 MHz or 400 MHz. So added support in mux to handle this condition. This patch series is based on renesas-clk-for-v5.15 [1] [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/?h=renesas-clk-for-v5.15 This patch series depend upon [2] [2] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=522063 Biju Das (2): drivers: clk: renesas: rzg2l-cpg: Add SDHI clk mux support drivers: clk: renesas: r9a07g044-cpg: Add SDHI clock and reset entries drivers/clk/renesas/r9a07g044-cpg.c | 37 ++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 106 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 12 ++++ 3 files changed, 155 insertions(+)