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[83.54.181.252]) by smtp.gmail.com with ESMTPSA id e14sm10801985wrw.33.2021.10.06.04.23.07 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Oct 2021 04:23:07 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH v2 0/4] clk: ralink: make system controller a reset provider Date: Wed, 6 Oct 2021 13:23:02 +0200 Message-Id: <20211006112306.4691-1-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi all, This patch series add minimal change to provide mt7621 resets properly defining them in the 'mediatek,mt7621-sysc' node which is the system controller of the SoC and is already providing clocks to the rest of the world. There is shared architecture code for all ralink platforms in 'reset.c' file located in 'arch/mips/ralink' but the correct thing to do to align hardware with software seems to define and add related reset code to the already mainlined clock driver. After this changes, we can get rid of the useless reset controller node in the device tree and use system controller node instead where the property '#reset-cells' has been added. Binding documentation for this nodeq has been updated with the new property accordly. This series also provide a bindings include header where all related reset bits for the MT7621 SoC are defined. Also, please take a look to this review [0] to understand better motivation for this series. Thanks in advance for your feedback. Changes in v2: - Address review comments of Dan Carpenter [1]: + Avoid 'inline' in function definition. + Return proper error codes (-EINVAL) instead of '-1'. + Make use of 'devm_kzalloc' instead of 'kzalloc'. Best regards, Sergio Paracuellos [0]: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20210926145931.14603-3-sergio.paracuellos@gmail.com/ [1]: https://lkml.org/lkml/2021/10/6/204 Sergio Paracuellos (4): dt-bindings: reset: add dt binding header for Mediatek MT7621 resets dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property clk: ralink: make system controller node a reset provider staging: mt7621-dts: align resets with binding documentation .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 +++ drivers/clk/ralink/clk-mt7621.c | 79 +++++++++++++++++++ drivers/staging/mt7621-dts/mt7621.dtsi | 27 +++---- include/dt-bindings/reset/mt7621-reset.h | 37 +++++++++ 4 files changed, 140 insertions(+), 15 deletions(-) create mode 100644 include/dt-bindings/reset/mt7621-reset.h