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(80.71.140.73.ipv4.parknet.dk. [80.71.140.73]) by smtp.gmail.com with ESMTPSA id y2sm3498451wmj.13.2022.01.26.09.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:40:21 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Andy Shevchenko , Geert Uytterhoeven , Arnd Bergmann , Michael Zhu , Fu Wei , linux-kernel@vger.kernel.org Subject: [PATCH v1 0/7] JH7100 Audio Clocks Date: Wed, 26 Jan 2022 18:39:46 +0100 Message-Id: <20220126173953.1016706-1-kernel@esmil.dk> X-Mailer: git-send-email 2.35.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This series add support for the audio clocks on the StarFive JH7100 RISC-V SoC, although the first two patches are fixes to the original addition of the basic clock driver. At least the first fix may be considered for 5.17. It turns out the SoC has several memory ranges for different clocks, but they all share the layout of the control registers. This could be modelled in 3 ways: 1) Model all the clocks as a single peripheral with multiple memory ranges and have a single driver for them all. 2) Model each memory range as different, but related peripherals with a single driver handling all of them. 3) Model each memory range as different peripherals with separate drivers that can share most code. Although the first option would require less code this series implements the 3rd option. The basic clock driver has to be built-in to boot the SoC, so separate drivers for the other registers means less code needs to be built-in and can be left as loadable modules. Emil Renner Berthing (7): clk: starfive: jh7100: Don't round divisor up twice clk: starfive: jh7100: Handle audio_div clock properly dt-bindings: clock: Add JH7100 audio clock definitions dt-bindings: clock: Add starfive,jh7100-audclk bindings clk: starfive: jh7100: Make hw clock implementation reusable clk: starfive: jh7100: Support more clock types clk: starfive: Add JH7100 audio clock driver .../clock/starfive,jh7100-audclk.yaml | 57 ++++++ MAINTAINERS | 8 +- drivers/clk/starfive/Kconfig | 8 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jh7100-audio.c | 170 +++++++++++++++++ drivers/clk/starfive/clk-starfive-jh7100.c | 176 +++++++++--------- drivers/clk/starfive/clk-starfive-jh7100.h | 112 +++++++++++ .../dt-bindings/clock/starfive-jh7100-audio.h | 41 ++++ 8 files changed, 482 insertions(+), 91 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml create mode 100644 drivers/clk/starfive/clk-starfive-jh7100-audio.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h create mode 100644 include/dt-bindings/clock/starfive-jh7100-audio.h