From patchwork Thu Mar 3 13:18:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 12767456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53E91C433EF for ; Thu, 3 Mar 2022 13:18:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232365AbiCCNTQ (ORCPT ); Thu, 3 Mar 2022 08:19:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230373AbiCCNTP (ORCPT ); Thu, 3 Mar 2022 08:19:15 -0500 Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [IPv6:2001:4b7a:2000:18::167]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50727149B8B; Thu, 3 Mar 2022 05:18:30 -0800 (PST) Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 4F3AD3F635; Thu, 3 Mar 2022 14:18:28 +0100 (CET) From: Marijn Suijten To: phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Pavel Dubrova , Marijn Suijten , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vamsi Krishna Lanka , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/3] clk: qcom: Add display clock controller driver for SM6125 Date: Thu, 3 Mar 2022 14:18:09 +0100 Message-Id: <20220303131812.302302-1-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Changes since v2: - dt-bindings: Use a sensible `&dsi1_phy 1` example clock for the mandatory "dsi1_phy_pll_out_dsiclk", instead of a null phandle. v2: https://lore.kernel.org/phone-devel/20220226200911.230030-1-marijn.suijten@somainline.org/ Changes since v1: - Documentation is dual-licensed; - Documentation example now uses zero-clock for dsi1_phy pixel clock; - SDX_GCC_65 is sorted in Kconfig/Makefile to easen adding this driver in the correct alphabetic spot; - clk.h is replaced with clk-provider.h; - ahb, mdp and rot source clocks use rcg2_shared_ops instead of standard ops; - Unnecessary line breaks are removed when remaining under 80 chars. v1: https://lore.kernel.org/linux-arm-msm/20211130212137.25303-1-martin.botka@somainline.org/T/#u Marijn Suijten (1): clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig Martin Botka (2): dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Add display clock controller driver for SM6125 .../bindings/clock/qcom,dispcc-sm6125.yaml | 87 +++ drivers/clk/qcom/Kconfig | 21 +- drivers/clk/qcom/Makefile | 3 +- drivers/clk/qcom/dispcc-sm6125.c | 709 ++++++++++++++++++ .../dt-bindings/clock/qcom,dispcc-sm6125.h | 41 + 5 files changed, 854 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml create mode 100644 drivers/clk/qcom/dispcc-sm6125.c create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm6125.h base-commit: e6ada6df471f847da3b09b357e246c62335bc0bb --- 2.35.1