From patchwork Sat Apr 2 07:46:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12799008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08040C433EF for ; Sat, 2 Apr 2022 07:46:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234787AbiDBHs0 (ORCPT ); Sat, 2 Apr 2022 03:48:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229776AbiDBHsY (ORCPT ); Sat, 2 Apr 2022 03:48:24 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1A97118B261; Sat, 2 Apr 2022 00:46:31 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.90,229,1643641200"; d="scan'208";a="115483885" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 02 Apr 2022 16:46:31 +0900 Received: from localhost.localdomain (unknown [10.226.92.166]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 91A6841E38A1; Sat, 2 Apr 2022 16:46:29 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH v2 0/4] Add GPIO,ETHERNET and SDHI Clock/Reset entries for RZ/G2UL Date: Sat, 2 Apr 2022 08:46:22 +0100 Message-Id: <20220402074626.25624-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch series aims to add GPIO, ETHERNET and SDHI Clock/Reset entries to RZ/G2UL Clk driver. This patch series depend upon [1] [1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=628396 v1->v2: * Added Rb tag from Geert Biju Das (4): clk: renesas: r9a07g043: Add GPIO clock and reset entries clk: renesas: r9a07g043: Add ethernet clock sources clk: renesas: r9a07g043: Add GbEthernet clock/reset clk: renesas: r9a07g043: Add SDHI clock and reset entries drivers/clk/renesas/r9a07g043-cpg.c | 63 +++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+)