| Message ID | 20220520100948.19622-1-johan+linaro@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | clk: qcom: gdsc: add support for collapse-vote registers | expand |
Please add Qualcomm on code for their hardware :) I did a translation from codeaurora but I don't know if Rajendra's will work. Quoting Johan Hovold (2022-05-20 03:09:45) > Recent Qualcomm platforms have APCS collapse-vote registers that allow > for sharing GDSCs with other masters (e.g. LPASS). How is it different from the voting logic that already exists in the gdsc file? Now every subsystem has to vote for off in addition to voting for on? > > Add support for using such vote registers instead of the control > register when updating the GDSC power state.
On Fri, May 20, 2022 at 08:51:09PM -0700, Stephen Boyd wrote: > Please add Qualcomm on code for their hardware :) > > I did a translation from codeaurora but I don't know if Rajendra's will > work. These addresses need to be added to .mailmap. > Quoting Johan Hovold (2022-05-20 03:09:45) > > Recent Qualcomm platforms have APCS collapse-vote registers that allow > > for sharing GDSCs with other masters (e.g. LPASS). > > How is it different from the voting logic that already exists in the > gdsc file? Now every subsystem has to vote for off in addition to voting > for on? No, the voting logic is unchanged (i.e. enabling by clearing a collapse bit). The difference is just that a separate register register is used for the voting. > > > > Add support for using such vote registers instead of the control > > register when updating the GDSC power state. Johan
Quoting Johan Hovold (2022-05-23 02:32:50) > On Fri, May 20, 2022 at 08:51:09PM -0700, Stephen Boyd wrote: > > Please add Qualcomm on code for their hardware :) > > > > I did a translation from codeaurora but I don't know if Rajendra's will > > work. > > These addresses need to be added to .mailmap. Patches welcome :) > > > Quoting Johan Hovold (2022-05-20 03:09:45) > > > Recent Qualcomm platforms have APCS collapse-vote registers that allow > > > for sharing GDSCs with other masters (e.g. LPASS). > > > > How is it different from the voting logic that already exists in the > > gdsc file? Now every subsystem has to vote for off in addition to voting > > for on? > > No, the voting logic is unchanged (i.e. enabling by clearing a collapse > bit). > > The difference is just that a separate register register is used for the > voting. > Ok. Got it.
On Fri, May 20, 2022 at 12:09:45PM +0200, Johan Hovold wrote: > Recent Qualcomm platforms have APCS collapse-vote registers that allow > for sharing GDSCs with other masters (e.g. LPASS). > > Add support for using such vote registers instead of the control > register when updating the GDSC power state. > > Note that the gcc-sc8280xp driver has not yet been merged. [1] The sc8280xp driver has been merged so this series could go in now. Bjorn? > [1] https://lore.kernel.org/all/20220505025457.1693716-1-bjorn.andersson@linaro.org/ > > > Johan Hovold (3): > clk: qcom: gdsc: add collapse-bit helper > clk: qcom: gdsc: add support for collapse-vote registers > clk: qcom: gcc-sc8280xp: use collapse-voting for PCIe GDSCs > > drivers/clk/qcom/gcc-sc8280xp.c | 21 +++++++++++++++++++++ > drivers/clk/qcom/gdsc.c | 28 ++++++++++++++++++++++------ > drivers/clk/qcom/gdsc.h | 4 ++++ > 3 files changed, 47 insertions(+), 6 deletions(-) Johan
On Fri, 20 May 2022 12:09:45 +0200, Johan Hovold wrote: > Recent Qualcomm platforms have APCS collapse-vote registers that allow > for sharing GDSCs with other masters (e.g. LPASS). > > Add support for using such vote registers instead of the control > register when updating the GDSC power state. > > Note that the gcc-sc8280xp driver has not yet been merged. [1] > > [...] Applied, thanks! [1/3] clk: qcom: gdsc: add collapse-bit helper commit: e73cb8527c597598599119fcd9c7d1752d9e9fd7 [2/3] clk: qcom: gdsc: add support for collapse-vote registers commit: 77ea2bd72da4f61f59ad2e839babe83849f35dea [3/3] clk: qcom: gcc-sc8280xp: use collapse-voting for PCIe GDSCs commit: 8d114b94fc39210b88b203b57aaf04836a87a4f0 Best regards,
Recent Qualcomm platforms have APCS collapse-vote registers that allow for sharing GDSCs with other masters (e.g. LPASS). Add support for using such vote registers instead of the control register when updating the GDSC power state. Note that the gcc-sc8280xp driver has not yet been merged. [1] Johan [1] https://lore.kernel.org/all/20220505025457.1693716-1-bjorn.andersson@linaro.org/ Johan Hovold (3): clk: qcom: gdsc: add collapse-bit helper clk: qcom: gdsc: add support for collapse-vote registers clk: qcom: gcc-sc8280xp: use collapse-voting for PCIe GDSCs drivers/clk/qcom/gcc-sc8280xp.c | 21 +++++++++++++++++++++ drivers/clk/qcom/gdsc.c | 28 ++++++++++++++++++++++------ drivers/clk/qcom/gdsc.h | 4 ++++ 3 files changed, 47 insertions(+), 6 deletions(-)