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([176.74.57.19]) by smtp.gmail.com with ESMTPSA id j10-20020a170906830a00b006f3ef214dc0sm682055ejx.38.2022.06.01.05.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 05:43:23 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v4 0/6] SM8350 Display/GPU clock enablement Date: Wed, 1 Jun 2022 14:42:44 +0200 Message-Id: <20220601124250.60968-1-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Changes since v2 - Dropped "clk: Introduce CLK_ASSUME_ENABLED_WHEN_UNUSED" - Dropped "clk: qcom: sm8250-dispcc: Flag shared RCGs as assumed enable" - Dropped "clk: qcom: rcg2: Cache rate changes for parked RCGs" Changes sinsce v3: - Dropped RBs & SoBs for bigger changes - Changed author to me for patches with big changes Robert Foss (6): arm64: dts: qcom: sm8350: Replace integers with rpmpd defines clk: qcom: add support for SM8350 GPUCC dt-bindings: clock: Add Qcom SM8350 GPUCC bindings clk: qcom: add support for SM8350 DISPCC dt-bindings: clock: Add Qcom SM8350 DISPCC bindings arm64: dts: qcom: sm8350: Add DISPCC node .../bindings/clock/qcom,dispcc-sm8350.yaml | 104 ++ .../bindings/clock/qcom,dispcc-sm8x50.yaml | 4 +- .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 + arch/arm64/boot/dts/qcom/sm8350.dtsi | 41 +- drivers/clk/qcom/Kconfig | 17 + drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/dispcc-sm8350.c | 1330 +++++++++++++++++ drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++ .../dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 + 10 files changed, 2250 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml create mode 100644 drivers/clk/qcom/dispcc-sm8350.c create mode 100644 drivers/clk/qcom/gpucc-sm8350.c create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h