From patchwork Tue Jun 21 16:11:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 12889497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B12B4C43334 for ; Tue, 21 Jun 2022 16:11:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353790AbiFUQLs (ORCPT ); Tue, 21 Jun 2022 12:11:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353786AbiFUQLs (ORCPT ); Tue, 21 Jun 2022 12:11:48 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED3F42CE21; Tue, 21 Jun 2022 09:11:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1655827907; x=1687363907; h=from:to:subject:date:message-id:mime-version; bh=VPMzRubPpLoq64j1JAqv7n1xLjw6zA0Rho5zPhkempo=; b=Z6vEHoofWF+96pf833YYzIV6hRAF26ptArD7ndCoIDGUo2tgC5VzgGh7 mpnKSQZr3UIRLcJrStik99viMPD0b0bHV79bUP1ymp8TW2sGGIuHbJDp4 6lbMUUeJNzzlgcO67iUZUEx2nCTd9rrYIdmkHSLZU6J1Mw6nHZcGNnUTY M=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 21 Jun 2022 09:11:46 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2022 09:11:46 -0700 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 21 Jun 2022 09:11:45 -0700 Received: from srichara-linux.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 21 Jun 2022 09:11:40 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , Subject: [PATCH V2 0/8] Add minimal boot support for IPQ5018 Date: Tue, 21 Jun 2022 21:41:18 +0530 Message-ID: <20220621161126.15883-1-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The IPQ5018 is Qualcomm's 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq5018-mp03.1-c2 board. [v2] Fixed all comments and rebased for TOT. Varadarajan Narayanan (8): clk: qcom: clk-alpha-pll: Add support for Stromer PLLs dt-bindings: arm64: ipq5018: Add binding descriptions for clock and reset clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 dt-bindings: pinctrl: qcom: Add ipq5018 pinctrl bindings pinctrl: qcom: Add IPQ5018 pinctrl driver dt-bindings: qcom: Add ipq5018 bindings arm64: dts: Add ipq5018 SoC and MP03 board support arm64: defconfig: Enable IPQ5018 SoC base configs .../devicetree/bindings/arm/qcom.yaml | 7 + .../bindings/clock/qcom,gcc-other.yaml | 3 + .../pinctrl/qcom,ipq5018-pinctrl.yaml | 145 + arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 29 + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 221 + arch/arm64/configs/defconfig | 3 + drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 100 +- drivers/clk/qcom/clk-alpha-pll.h | 7 +- drivers/clk/qcom/gcc-ipq5018.c | 3995 +++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5018.c | 791 ++++ include/dt-bindings/clock/qcom,gcc-ipq5018.h | 188 + include/dt-bindings/reset/qcom,gcc-ipq5018.h | 122 + 17 files changed, 5629 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq5018.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h