From patchwork Mon Aug 22 11:29:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12950523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1868DC32789 for ; Mon, 22 Aug 2022 11:30:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234284AbiHVL37 (ORCPT ); Mon, 22 Aug 2022 07:29:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234170AbiHVL36 (ORCPT ); Mon, 22 Aug 2022 07:29:58 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A024D33349; Mon, 22 Aug 2022 04:29:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661167797; x=1692703797; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=RJ04Kh5e1eZ1WoCexWG+Naw0DQ2en6wdmxTB7LzJfB4=; b=WYFdwjaQzwiZoh+S9vNJBjfc/HO0JxggjnYtSNiBAFLbYZQS+KV/OtW1 cAjmsuhgHq+rzgWi808rnkhaCeQHOBiICZs8P1SzOAKZGCo8ENPXaIUAM /SsgXFH0r07lvqmL7ECB5ke0PX+kYiAuzQa0grlAZqhJQVYn0yQ8367Gk XnHBh4BiqRevNV/PcwvSypiV+WzdsxCvtz/AilxWbV43OYSobCWzuRzbg zMr8DL6d4GQgXnDUl5eUjFtqxunFsrYn36w6vWUJhxTG81NMMewrbv7YK Rgd0Hy/WZbEBF5aez7mX3HKl55xgtxIIntQH+l7K7tDXN3NfC+YUCNjAd Q==; X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="110092089" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Aug 2022 04:29:56 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 22 Aug 2022 04:29:54 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 22 Aug 2022 04:29:51 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara , Hugh Breslin CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 0/6] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support Date: Mon, 22 Aug 2022 12:29:23 +0100 Message-ID: <20220822112928.2727437-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hey all, PolarFire SoC has 4 clock source blocks, each with 2 PLLs and 2 DLLs, in the corners of the FPGA fabric. Add bindings, a driver supporting the PLLs and the requisite changes to the devicetrees for PolarFire SoC based boards. These clocks were already in use, but which clock specifically was chosen was decided by the synthesis tool. In our end-of-September release of our FPGA reference design, constraints will be added to force the synthesis tool to pick the "north west" CCC, making it possible to read the configuration from the CCC's registers. I am mainly looking for feedback on the dt-bindings on this version, so that if something dt-abi related needs to change it can be done in advance. There are no maintainers changes in this series, but they are required due to the binding rename. I am waiting for some changes queued in the soc tree before rebasing on a later -rc before including that patch. Thanks, Conor. Changes since v1: - Stopped using the dt node name to generate the clk name. Rather than use clock-output-names etc, I just opted to call each PLL after it's individual base address: cccrefclk ccc@38100000_pll0 ccc@38100000_pll0_out3 ccc@38100000_pll0_out2 ccc@38100000_pll0_out1 ccc@38100000_pll0_out0 - dt nodes are now all called "clock-controller" Conor Dooley (6): dt-bindings: clk: rename mpfs-clkcfg binding dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: add PolarFire SoC fabric clock ids clk: microchip: add PolarFire SoC fabric clock support dt-bindings: riscv: microchip: document icicle reference design riscv: dts: microchip: add the mpfs' fabric clock control .../bindings/clock/microchip,mpfs-ccc.yaml | 81 +++++ ...p,mpfs.yaml => microchip,mpfs-clkcfg.yaml} | 2 +- .../devicetree/bindings/riscv/microchip.yaml | 1 + .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 27 +- .../boot/dts/microchip/mpfs-icicle-kit.dts | 4 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 5 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 34 +- drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk-mpfs-ccc.c | 293 ++++++++++++++++++ .../dt-bindings/clock/microchip,mpfs-clock.h | 23 ++ 10 files changed, 458 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml rename Documentation/devicetree/bindings/clock/{microchip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} (96%) create mode 100644 drivers/clk/microchip/clk-mpfs-ccc.c base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868