From patchwork Wed Aug 24 09:33:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12953103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F14EC3F6B0 for ; Wed, 24 Aug 2022 09:34:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229884AbiHXJeV (ORCPT ); Wed, 24 Aug 2022 05:34:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229542AbiHXJeT (ORCPT ); Wed, 24 Aug 2022 05:34:19 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAA9984EEA; Wed, 24 Aug 2022 02:34:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661333659; x=1692869659; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6/9bHIY/hzWRwp2EdYp1b9h1WrFSvYNmvafvDtchgVc=; b=nVmxz3Y1XaQOI2khhhVGrkwXxOhKeKZ7PHDE0XE9vueKmqsIColtmJpe m/2R2d3KTGnEKeDtqOzh1i9Hiym0VYRWHoY+OsGZffq2pwN+g5KiVLYGX dfdOdMmim2lNzfHCIRENuJA9Z0K1H4LMO5H8TpCNcf1MGf0JGrM23QZ3+ 5nDx3zGdu/2WKKBHx3qSY+uWXHdwCSiQaP9GOsDC419atc6fl8tSEPf4n s4hn+SOVOi/rYFtlGDsq+uPlaFnFXeyi8szwX5yetTrNkXPuXW2hN7Vs0 5ft+sw9S3d0LfSFGaXjOR0X/Pgx75M8cmjSecTG83TdgEgAUFDSN+qQNW A==; X-IronPort-AV: E=Sophos;i="5.93,260,1654585200"; d="scan'208";a="170697507" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Aug 2022 02:34:19 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 24 Aug 2022 02:34:17 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 24 Aug 2022 02:34:14 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara , Hugh Breslin CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 0/5] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support Date: Wed, 24 Aug 2022 10:33:38 +0100 Message-ID: <20220824093342.187844-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hey all, PolarFire SoC has 4 clock source blocks, each with 2 PLLs and 2 DLLs, in the corners of the FPGA fabric. Add bindings, a driver supporting the PLLs and the requisite changes to the devicetrees for PolarFire SoC based boards. These clocks were already in use, but which clock specifically was chosen was decided by the synthesis tool. In our end-of-September release of our FPGA reference design, constraints will be added to force the synthesis tool to pick the "north west" CCC, making it possible to read the configuration from the CCC's registers. I am mainly looking for feedback on the dt-bindings on this version, so that if something dt-abi related needs to change it can be done in advance. There are no maintainers changes in this series, but they are required due to the binding rename. I am waiting for some changes queued in the soc tree before rebasing on a later -rc before including that patch. Thanks, Conor. Changes since v2: - Removed the unintentionaly leftover clock-output-names - Dropped the riscv/microchip dt-binding update. I am moving it to another series for the dts, which is likely to be applied first so it does not depend on this series. Changes since v1: - Stopped using the dt node name to generate the clk name. Rather than use clock-output-names etc, I just opted to call each PLL after it's individual base address: cccrefclk ccc@38100000_pll0 ccc@38100000_pll0_out3 ccc@38100000_pll0_out2 ccc@38100000_pll0_out1 ccc@38100000_pll0_out0 - dt nodes are now all called "clock-controller" Conor Dooley (5): dt-bindings: clk: rename mpfs-clkcfg binding dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: add PolarFire SoC fabric clock ids clk: microchip: add PolarFire SoC fabric clock support riscv: dts: microchip: add the mpfs' fabric clock control .../bindings/clock/microchip,mpfs-ccc.yaml | 80 +++++ ...p,mpfs.yaml => microchip,mpfs-clkcfg.yaml} | 2 +- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 27 +- .../boot/dts/microchip/mpfs-icicle-kit.dts | 4 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 5 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 34 +- drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk-mpfs-ccc.c | 293 ++++++++++++++++++ .../dt-bindings/clock/microchip,mpfs-clock.h | 23 ++ 9 files changed, 456 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml rename Documentation/devicetree/bindings/clock/{microchip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} (96%) create mode 100644 drivers/clk/microchip/clk-mpfs-ccc.c base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868