| Message ID | 20230206103337.21000-1-quic_devipriy@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add minimal boot support for IPQ9574 | expand |
On 06/02/2023 12:33, Devi Priya wrote: > Add Global Clock Controller (GCC) driver for ipq9574 based devices > > Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > Changes in V7: > - Used qcom_cc_probe instead of qcom_cc_really_probe in > gcc_ipq9574_probe > > drivers/clk/qcom/Kconfig | 8 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-ipq9574.c | 4295 ++++++++++++++++++++++++++++++++ > 3 files changed, 4304 insertions(+) > create mode 100644 drivers/clk/qcom/gcc-ipq9574.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 5ab4b7dfe3c2..a9f01d67a500 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -173,6 +173,14 @@ config IPQ_GCC_8074 > i2c, USB, SD/eMMC, etc. Select this for the root clock > of ipq8074. > > +config IPQ_GCC_9574 > + tristate "IPQ9574 Global Clock Controller" > + help > + Support for global clock controller on ipq9574 devices. > + Say Y if you want to use peripheral devices such as UART, SPI, > + i2c, USB, SD/eMMC, etc. Select this for the root clock > + of ipq9574. > + > config MSM_GCC_8660 > tristate "MSM8660 Global Clock Controller" > help > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 3194465dd02c..51e6e5eb187b 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o > obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o > obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o > obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o > +obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o > obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o > obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o > obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c > new file mode 100644 > index 000000000000..718106a9ac7b > --- /dev/null > +++ b/drivers/clk/qcom/gcc-ipq9574.c [skipped] > +static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = { > + .halt_reg = 0x2e054, > + .clkr = { > + .enable_reg = 0x2e054, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data) { > + .name = "gcc_snoc_pcie3_2lane_s_clk", > + .parent_hws = (const struct clk_hw *[]) { > + &pcie3_axi_s_clk_src.clkr.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_regmap_mux pcie0_pipe_clk_src = { > + .reg = 0x28064, > + .shift = 8, > + .width = 2, > + .parent_map = gcc_pcie30_phy0_pipe_clk_xo_map, > + .clkr = { > + .hw.init = &(struct clk_init_data) { > + .name = "pcie0_pipe_clk_src", > + .parent_data = gcc_pcie30_phy0_pipe_clk_xo, > + .num_parents = ARRAY_SIZE(gcc_pcie30_phy0_pipe_clk_xo), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_mux_closest_ops, clk_regmap_phy_mux_ops ? > + }, > + }, > +}; > + > +static struct clk_regmap_mux pcie1_pipe_clk_src = { > + .reg = 0x29064, > + .shift = 8, > + .width = 2, > + .parent_map = gcc_pcie30_phy1_pipe_clk_xo_map, > + .clkr = { > + .hw.init = &(struct clk_init_data) { > + .name = "pcie1_pipe_clk_src", > + .parent_data = gcc_pcie30_phy1_pipe_clk_xo, > + .num_parents = ARRAY_SIZE(gcc_pcie30_phy1_pipe_clk_xo), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_mux_closest_ops, > + }, > + }, > +}; > + > +static struct clk_regmap_mux pcie2_pipe_clk_src = { > + .reg = 0x2a064, > + .shift = 8, > + .width = 2, > + .parent_map = gcc_pcie30_phy2_pipe_clk_xo_map, > + .clkr = { > + .hw.init = &(struct clk_init_data) { > + .name = "pcie2_pipe_clk_src", > + .parent_data = gcc_pcie30_phy2_pipe_clk_xo, > + .num_parents = ARRAY_SIZE(gcc_pcie30_phy2_pipe_clk_xo), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_mux_closest_ops, clk_regmap_phy_mux_ops ? > + }, > + }, > +}; > + > +static struct clk_regmap_mux pcie3_pipe_clk_src = { > + .reg = 0x2b064, > + .shift = 8, > + .width = 2, > + .parent_map = gcc_pcie30_phy3_pipe_clk_xo_map, > + .clkr = { > + .hw.init = &(struct clk_init_data) { > + .name = "pcie3_pipe_clk_src", > + .parent_data = gcc_pcie30_phy3_pipe_clk_xo, > + .num_parents = ARRAY_SIZE(gcc_pcie30_phy3_pipe_clk_xo), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_mux_closest_ops, clk_regmap_phy_mux_ops ? > + }, > + }, > +};
Thanks for taking time to review the patch! On 2/6/2023 7:37 PM, Dmitry Baryshkov wrote: > On 06/02/2023 12:33, Devi Priya wrote: >> Add Global Clock Controller (GCC) driver for ipq9574 based devices >> >> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> Changes in V7: >> - Used qcom_cc_probe instead of qcom_cc_really_probe in >> gcc_ipq9574_probe >> >> drivers/clk/qcom/Kconfig | 8 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/gcc-ipq9574.c | 4295 ++++++++++++++++++++++++++++++++ >> 3 files changed, 4304 insertions(+) >> create mode 100644 drivers/clk/qcom/gcc-ipq9574.c >> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index 5ab4b7dfe3c2..a9f01d67a500 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -173,6 +173,14 @@ config IPQ_GCC_8074 >> i2c, USB, SD/eMMC, etc. Select this for the root clock >> of ipq8074. >> +config IPQ_GCC_9574 >> + tristate "IPQ9574 Global Clock Controller" >> + help >> + Support for global clock controller on ipq9574 devices. >> + Say Y if you want to use peripheral devices such as UART, SPI, >> + i2c, USB, SD/eMMC, etc. Select this for the root clock >> + of ipq9574. >> + >> config MSM_GCC_8660 >> tristate "MSM8660 Global Clock Controller" >> help >> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile >> index 3194465dd02c..51e6e5eb187b 100644 >> --- a/drivers/clk/qcom/Makefile >> +++ b/drivers/clk/qcom/Makefile >> @@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o >> obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o >> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o >> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o >> +obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o >> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o >> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o >> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o >> diff --git a/drivers/clk/qcom/gcc-ipq9574.c >> b/drivers/clk/qcom/gcc-ipq9574.c >> new file mode 100644 >> index 000000000000..718106a9ac7b >> --- /dev/null >> +++ b/drivers/clk/qcom/gcc-ipq9574.c > > [skipped] > >> +static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = { >> + .halt_reg = 0x2e054, >> + .clkr = { >> + .enable_reg = 0x2e054, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data) { >> + .name = "gcc_snoc_pcie3_2lane_s_clk", >> + .parent_hws = (const struct clk_hw *[]) { >> + &pcie3_axi_s_clk_src.clkr.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux pcie0_pipe_clk_src = { >> + .reg = 0x28064, >> + .shift = 8, >> + .width = 2, >> + .parent_map = gcc_pcie30_phy0_pipe_clk_xo_map, >> + .clkr = { >> + .hw.init = &(struct clk_init_data) { >> + .name = "pcie0_pipe_clk_src", >> + .parent_data = gcc_pcie30_phy0_pipe_clk_xo, >> + .num_parents = ARRAY_SIZE(gcc_pcie30_phy0_pipe_clk_xo), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_regmap_mux_closest_ops, > > > clk_regmap_phy_mux_ops ? Okay, will update the ops and struct accordingly in the next series > >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux pcie1_pipe_clk_src = { >> + .reg = 0x29064, >> + .shift = 8, >> + .width = 2, >> + .parent_map = gcc_pcie30_phy1_pipe_clk_xo_map, >> + .clkr = { >> + .hw.init = &(struct clk_init_data) { >> + .name = "pcie1_pipe_clk_src", >> + .parent_data = gcc_pcie30_phy1_pipe_clk_xo, >> + .num_parents = ARRAY_SIZE(gcc_pcie30_phy1_pipe_clk_xo), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_regmap_mux_closest_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux pcie2_pipe_clk_src = { >> + .reg = 0x2a064, >> + .shift = 8, >> + .width = 2, >> + .parent_map = gcc_pcie30_phy2_pipe_clk_xo_map, >> + .clkr = { >> + .hw.init = &(struct clk_init_data) { >> + .name = "pcie2_pipe_clk_src", >> + .parent_data = gcc_pcie30_phy2_pipe_clk_xo, >> + .num_parents = ARRAY_SIZE(gcc_pcie30_phy2_pipe_clk_xo), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_regmap_mux_closest_ops, > > clk_regmap_phy_mux_ops ? Okay > > >> + }, >> + }, >> +}; >> + >> +static struct clk_regmap_mux pcie3_pipe_clk_src = { >> + .reg = 0x2b064, >> + .shift = 8, >> + .width = 2, >> + .parent_map = gcc_pcie30_phy3_pipe_clk_xo_map, >> + .clkr = { >> + .hw.init = &(struct clk_init_data) { >> + .name = "pcie3_pipe_clk_src", >> + .parent_data = gcc_pcie30_phy3_pipe_clk_xo, >> + .num_parents = ARRAY_SIZE(gcc_pcie30_phy3_pipe_clk_xo), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_regmap_mux_closest_ops, > > clk_regmap_phy_mux_ops ? Okay > >> + }, >> + }, >> +}; > Best Regards, Devi Priya