| Message ID | 20230314124404.117592-1-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add new partial clock and reset drivers for StarFive JH7110 | expand |
Quoting Xingyu Wu (2023-03-14 05:43:53) > This patch serises are to add new partial clock drivers and reset > supports about System-Top-Group(STG), Image-Signal-Process(ISP) > and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. What is your merge plan for this series? Did you intend for clk tree to take the majority of patches? We won't take the dts changes through the clk tree. I think Philipp Zabel reviewed some earlier version of the patches and provided reviewed-by tags. Can you check if they can be added here? If so, please resend again, or get those merged through the reset tree.
On 2023/3/15 8:30, Stephen Boyd wrote: > Quoting Xingyu Wu (2023-03-14 05:43:53) >> This patch serises are to add new partial clock drivers and reset >> supports about System-Top-Group(STG), Image-Signal-Process(ISP) >> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. > > What is your merge plan for this series? Did you intend for clk tree to > take the majority of patches? We won't take the dts changes through the > clk tree. > > I think Philipp Zabel reviewed some earlier version of the patches and > provided reviewed-by tags. Can you check if they can be added here? If > so, please resend again, or get those merged through the reset tree. These patches add new clock & reset providers based on the basic clock & reset of the minimal system which Hal.feng had submitted[1], which are used in USB, DMA, VIN and Display modules that are merging. [1]: https://lore.kernel.org/all/20230311090733.56918-1-hal.feng@starfivetech.com/ Oh I checked and had not received any comments from Philipp Zabel in earlier version of these patches. Maybe it was confused with the patches of the minimal system. Best regards, Xingyu Wu
Hey Stephen, On Wed, Mar 15, 2023 at 11:44:00AM +0800, Xingyu Wu wrote: > On 2023/3/15 8:30, Stephen Boyd wrote: > > Quoting Xingyu Wu (2023-03-14 05:43:53) > >> This patch serises are to add new partial clock drivers and reset > >> supports about System-Top-Group(STG), Image-Signal-Process(ISP) > >> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. > > > > What is your merge plan for this series? Did you intend for clk tree to > > take the majority of patches? We won't take the dts changes through the > > clk tree. FWIW, I've been waiting for the "main" clock/reset series [1] to be ready to go, before suggesting that I take it (the main series) via the soc tree. This one is kinda in the same boat, with defines in the dt-binding headers that are used by both drivers and dts, so splitting the two doesn't make all that much sense. As Xingyu points out below, this series depends on the main one, so if I was to take that via soc, this one would need to go on top, or be delayed. At what point does that become too much to go via soc and some sort of shared tag become needed? Thanks, Conor. > > > > I think Philipp Zabel reviewed some earlier version of the patches and > > provided reviewed-by tags. Can you check if they can be added here? If > > so, please resend again, or get those merged through the reset tree. > > These patches add new clock & reset providers based on the basic clock & reset > of the minimal system which Hal.feng had submitted[1], which are used in USB, DMA, > VIN and Display modules that are merging. [1]: https://lore.kernel.org/all/20230311090733.56918-1-hal.feng@starfivetech.com/ > > Oh I checked and had not received any comments from Philipp Zabel in earlier version > of these patches. Maybe it was confused with the patches of the minimal system. > > Best regards, > Xingyu Wu
Quoting Conor Dooley (2023-03-15 01:14:06) > Hey Stephen, > > On Wed, Mar 15, 2023 at 11:44:00AM +0800, Xingyu Wu wrote: > > On 2023/3/15 8:30, Stephen Boyd wrote: > > > Quoting Xingyu Wu (2023-03-14 05:43:53) > > >> This patch serises are to add new partial clock drivers and reset > > >> supports about System-Top-Group(STG), Image-Signal-Process(ISP) > > >> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. > > > > > > What is your merge plan for this series? Did you intend for clk tree to > > > take the majority of patches? We won't take the dts changes through the > > > clk tree. > > FWIW, I've been waiting for the "main" clock/reset series [1] to be ready > to go, before suggesting that I take it (the main series) via the soc > tree. This one is kinda in the same boat, with defines in the dt-binding > headers that are used by both drivers and dts, so splitting the two > doesn't make all that much sense. > > As Xingyu points out below, this series depends on the main one, so if I > was to take that via soc, this one would need to go on top, or be > delayed. > At what point does that become too much to go via soc and some sort of > shared tag become needed? > Platform/SoC maintainers either base their DTS file branch on some branch made in clk repo that has the bindings and drivers they need (clk-starfive probably), or they send a pull request to clk maintainers with the bindings and clk drivers. Or they don't use the #defines in the header files and use raw numbers in the DTS, or they simply apply the patch that just has the #defines in it to their SoC tree and we duplicate the commit in the history by also applying it to the clk tree. Let's try to keep things simple and not use raw numbers. BTW, clk driver code doesn't typically go via soc. Not sure if that's happening but please don't do that.
Quoting Xingyu Wu (2023-03-14 20:44:00) > On 2023/3/15 8:30, Stephen Boyd wrote: > > Quoting Xingyu Wu (2023-03-14 05:43:53) > >> This patch serises are to add new partial clock drivers and reset > >> supports about System-Top-Group(STG), Image-Signal-Process(ISP) > >> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. > > > > What is your merge plan for this series? Did you intend for clk tree to > > take the majority of patches? We won't take the dts changes through the > > clk tree. > > > > I think Philipp Zabel reviewed some earlier version of the patches and > > provided reviewed-by tags. Can you check if they can be added here? If > > so, please resend again, or get those merged through the reset tree. > > These patches add new clock & reset providers based on the basic clock & reset > of the minimal system which Hal.feng had submitted[1], which are used in USB, DMA, > VIN and Display modules that are merging. > [1]: https://lore.kernel.org/all/20230311090733.56918-1-hal.feng@starfivetech.com/ > > Oh I checked and had not received any comments from Philipp Zabel in earlier version > of these patches. Maybe it was confused with the patches of the minimal system. > Ok. I am waiting for a resend on that series from Hal.feng
On Wed, Mar 15, 2023 at 03:40:00PM -0700, Stephen Boyd wrote: > Quoting Conor Dooley (2023-03-15 01:14:06) > > At what point does that become too much to go via soc and some sort of > > shared tag become needed? > BTW, clk driver code doesn't typically go via soc. Not sure if that's > happening but please don't do that. Perfect, shan't. > Platform/SoC maintainers either base their DTS file branch on some > branch made in clk repo that has the bindings and drivers they need > (clk-starfive probably), or they send a pull request to clk maintainers > with the bindings and clk drivers. Or they don't use the #defines in the > header files and use raw numbers in the DTS, or they simply apply the > patch that just has the #defines in it to their SoC tree and we > duplicate the commit in the history by also applying it to the clk tree. > > Let's try to keep things simple and not use raw numbers. Definitely not! I'll do something sane with Emil once the base series is ready. Just was not sure how you typically liked this stuff to go, and now I am sure of what you do not want! Thanks, Conor.
This patch serises are to add new partial clock drivers and reset supports about System-Top-Group(STG), Image-Signal-Process(ISP) and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. Patches 1 to 3 are about the System-Top-Group clock and reset generator(STGCRG) part. The first patch adds docunmentation to describe STG bindings, and the second patch adds support about STG resets. The last patch adds clock driver to support STG clocks for JH7110. Patches 4 to 6 are about the Image-Signal-Process clock and reset gennerator(ISPCRG) part. The first patch adds docunmentation to describe ISP bindings, and the second patch adds support about ISP resets. The last patch adds clock driver to support ISP clocks for JH7110. Patches 7 to 9 are about the Video-Output clock and reset generator(VOUTCRG) part. The first patch adds docunmentation to describe VOUT bindings, and the second patch adds support about VOUT resets. The last patch adds clock driver to support VOUT clocks for JH7110. Patch 10 adds external clocks which ISP and VOUT clock driver need. Patch 11 adds device node about STGCRG, ISPCRG and VOUTCRG to JH7110 dts. Patches 2, 3, 5, 6, 8 and 9 are dependent on the patchset [1] which is about JH71x0 clock and reset driver. Patchdes 10 and 11 are dependent on the patchset [1] and [2] which is about JH7110 device tree and PMU node. This patchset should be applied after the patchset [1], [2]: [1] https://lore.kernel.org/all/20230311090733.56918-1-hal.feng@starfivetech.com/ [2] https://lore.kernel.org/all/20230116074259.22874-4-walker.chen@starfivetech.com/ Changes since v2: Patch 1: - Dropped the modification of maintainers. - Modified clock and reset names in the dt-bindings header files. Patch 3: - Added 'Emil Renner Berthing' as the author. - Used 'default m' in Kconfig file. - Changed the flags of 'CLK_IGNORE_UNUSED' to 0 or 'CLK_IS_CRITICAL'. Patch 4: - Dropped the 'reset-names' property. - Shortened the clock and reset names in the dt-bindings header files. Pacth 6: - Used 'default m' in Kconfig file. - Changed the flags of 'CLK_IGNORE_UNUSED' to 0. - Set reset_control struct to a local variable because it just is used one time in probe. Pacth 7: - Dropped the 'reset-names' property. Patch 9: - Used 'default m' in Kconfig file. - Set reset_control struct to a local variable because it just is used one time in probe. Patch 10: - Changed the order of externel clock in alphanumerical order. Patch 11: - Dropped the 'reset-names' property in ispcrg and voutcrg node. v2:https://lore.kernel.org/all/20230221083323.302471-1-xingyu.wu@starfivetech.com/ Changes since v1: - Modified the binding and dropped the indentation. - Removed the useless header files in the drivers. - Used an array lookup instead of a pile of conditions about parent clocks' name. - Added clocks operation on driver remove. v1: https://lore.kernel.org/all/20230120024445.244345-1-xingyu.wu@starfivetech.com/ Emil Renner Berthing (1): clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu (10): dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator reset: starfive: jh7110: Add StarFive System-Top-Group reset support dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator reset: starfive: jh7110: Add StarFive Image-Signal-Process reset support clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator reset: starfive: jh7110: Add StarFive Video-Output reset support clk: starfive: Add StarFive JH7110 Video-Output clock driver riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes .../clock/starfive,jh7110-ispcrg.yaml | 87 +++++++ .../clock/starfive,jh7110-stgcrg.yaml | 82 ++++++ .../clock/starfive,jh7110-voutcrg.yaml | 90 +++++++ .../jh7110-starfive-visionfive-2.dtsi | 8 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 67 +++++ drivers/clk/starfive/Kconfig | 33 +++ drivers/clk/starfive/Makefile | 3 + .../clk/starfive/clk-starfive-jh7110-isp.c | 233 +++++++++++++++++ .../clk/starfive/clk-starfive-jh7110-stg.c | 176 +++++++++++++ .../clk/starfive/clk-starfive-jh7110-vout.c | 240 ++++++++++++++++++ .../reset/starfive/reset-starfive-jh7110.c | 30 +++ .../dt-bindings/clock/starfive,jh7110-crg.h | 74 ++++++ .../dt-bindings/reset/starfive,jh7110-crg.h | 60 +++++ 13 files changed, 1183 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-isp.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-stg.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-vout.c base-commit: 8ca09d5fa3549d142c2080a72a4c70ce389163cd prerequisite-patch-id: ebaead89601acf604e83224f4df8d57a7f4331b8 prerequisite-patch-id: 609d5d7c55b0b8e2967966673dab8f62a6fceab9 prerequisite-patch-id: ac150a8c622e858e088df8121093d448df49c245 prerequisite-patch-id: a4255724d4698f1238663443024de56de38d717b prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d prerequisite-patch-id: dfb8d5a1fb262127d7a8e1ef3e97f455aaa19509 prerequisite-patch-id: 11b0f5746bbfbf8aa5c5746dcd7b0dce62e7f922 prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16 prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172 prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067 prerequisite-patch-id: 189a0f41ba4eecd4f3f35c503baac8aed8ccd7de prerequisite-patch-id: 1117ecaa40a353c667b71802ab34ecf9568d8bb2 prerequisite-patch-id: 25923a0c77e92631ed3cd8a163d789daad35f0f8 prerequisite-patch-id: 6a6f6215f09932e68fdfd294df2e813ec9d2481f prerequisite-patch-id: 2cc95b47cad25fd9b875d27f4e8e3d84eb70274b prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9 prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b prerequisite-patch-id: e7773c977a7b37692e9792b21cc4f17fa58f9215 prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd prerequisite-patch-id: 0a0ac5a8a90655b415f6b62e324f3db083cdaaee prerequisite-patch-id: 2ddada18ab6ea5cd1da14212aaf59632f5203d40