[v2,0/2] clk: sunxi-ng: Consider alternative parent rates when determining NKM clock rate

Message

Frank Oltmanns June 11, 2023, 9:01 a.m. UTC

This is V2 of a patchset that enables NKM clocks to consider alternative parent
rates and utilize this new feature to adjust the pll-video0 clock on Allwinner
A64.

This allows to achieve an optimal rate for driving the board's panel.

To provide some context, the clock structure involved in this process is as follows:
    clock                       clock type
    --------------------------------------
    pll-video0                  ccu_nm
       pll-mipi                 ccu_nkm
          tcon0                 ccu_mux
             tcon-data-clock    sun4i_dclk

The divider between tcon0 and tcon-data-clock is fixed at 4. Therefore, in order
to achieve a rate that closely matches the desired rate of the panel, pll-mipi
needs to operate at a specific rate.

Changes in V2:
 - Move optimal parent rate calculation to dedicated function
 - Choose a parent rate that does not to overshoot requested rate
 - Add comments to ccu_nkm_find_best
 - Make sure that best_parent_rate stays at original parent rate in the unlikely
   case that all combinations overshoot.

Link to V1:
https://lore.kernel.org/lkml/[e-mail]/

Frank Oltmanns (2):
  clk: sunxi-ng: nkm: consider alternative parent rates when finding
    rate
  clk: sunxi-ng: a64: allow pll-mipi to set parent's rate

 drivers/clk/sunxi-ng/ccu-sun50i-a64.c |  3 +-
 drivers/clk/sunxi-ng/ccu_nkm.c        | 66 +++++++++++++++++++++++----
 2 files changed, 60 insertions(+), 9 deletions(-)