Message ID | 20230809080047.19877-1-quic_luoj@quicinc.com (mailing list archive) |
---|---|
Headers | show |
Series | add clock controller of qca8386/qca8084 | expand |
On 09/08/2023 10:00, Luo Jie wrote: > qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode > named by qca8386, or working as PHY mode named by qca8084, > clock hardware reigster is accessed by MDIO bus. > > This patch series add the clock controller of qca8363/qca8084, > and add the clock ops clk_branch2_qca8k_ops to avoid spin lock > used during the clock operation of qca8k clock controller where > the sleep happens when accessing clock control register by MDIO > bus. > > Changes in v1: > * remove clock flag CLK_ENABLE_MUTEX_LOCK. > * add clock ops clk_branch2_qca8k_ops. > * improve yaml file for fixing dtschema warnings. > * enable clock controller driver in defconfig. So this is v2, not v1. Your next version, if happens, will be v3, please. Best regards, Krzysztof
On 8/9/2023 11:32 PM, Krzysztof Kozlowski wrote: > On 09/08/2023 10:00, Luo Jie wrote: >> qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode >> named by qca8386, or working as PHY mode named by qca8084, >> clock hardware reigster is accessed by MDIO bus. >> >> This patch series add the clock controller of qca8363/qca8084, >> and add the clock ops clk_branch2_qca8k_ops to avoid spin lock >> used during the clock operation of qca8k clock controller where >> the sleep happens when accessing clock control register by MDIO >> bus. >> >> Changes in v1: >> * remove clock flag CLK_ENABLE_MUTEX_LOCK. >> * add clock ops clk_branch2_qca8k_ops. >> * improve yaml file for fixing dtschema warnings. >> * enable clock controller driver in defconfig. > > So this is v2, not v1. Your next version, if happens, will be v3, please. > > Best regards, > Krzysztof > got it, i will use V3 in the next patch set, thanks Krzysztof.