From patchwork Tue Aug 15 08:52:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13353660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74DEAC04FE1 for ; Tue, 15 Aug 2023 08:53:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235785AbjHOIxF (ORCPT ); Tue, 15 Aug 2023 04:53:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235789AbjHOIwr (ORCPT ); Tue, 15 Aug 2023 04:52:47 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E43F19BC; Tue, 15 Aug 2023 01:52:41 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37F7A9eV028826; Tue, 15 Aug 2023 08:52:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=Kt3iFDmr8ZJ/XYq+so82jFjoXDuIgsJ3If0n1u9Tvy0=; b=AdkTIVDJQGDr4+D1pwUHFFCtV6JnJY387h/KZYUj4zjaw74KexeApU4vcTWydPuAwk9P K9YURbQ6yqitDgvPCEWDclcHXe2sdfFqhzeWhS2K441m6I9G3Sqg1GGYAg767/9F+ZHv Nqv71bvifQF9TdyGaTAHPv4xZ16fbb75X/8JVE3xShBXWrlX79rKdvmojb4Dyg12QX2C ppIGeSc6pZ3bW5Qjp9mRZQlnnkD7neSoi4gm7VAhAveThptI/6wa/97YRsl40hvhDDIe VFGu/7jaK/uP36867eYG0MWQkqENTxN/6Gsc9UBlrC1n9ETecwNli4kz88OZBGGCL6Mc ZQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3sfqp1hdey-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 15 Aug 2023 08:52:25 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37F8qOrq025648 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 15 Aug 2023 08:52:24 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 15 Aug 2023 01:52:20 -0700 From: Luo Jie To: , , , , , , , , , , CC: , , , , , Luo Jie Subject: [PATCH v4 0/4] add clock controller of qca8386/qca8084 Date: Tue, 15 Aug 2023 16:52:01 +0800 Message-ID: <20230815085205.9868-1-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: t5ORGL9dUWFDyV2fzh0CI5Bn_rwqQ_kN X-Proofpoint-ORIG-GUID: t5ORGL9dUWFDyV2fzh0CI5Bn_rwqQ_kN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-15_08,2023-08-10_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 mlxlogscore=957 bulkscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 mlxscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308150079 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode named by qca8386, or working as PHY mode named by qca8084, clock hardware reigster is accessed by MDIO bus. This patch series add the clock controller of qca8363/qca8084, and add the clock ops clk_branch2_mdio_ops to avoid spin lock used during the clock operation of qca8k clock controller where the sleep happens when accessing clock control register by MDIO bus. Changes in v2: * remove clock flag CLK_ENABLE_MUTEX_LOCK. * add clock ops clk_branch2_qca8k_ops. * improve yaml file for fixing dtschema warnings. * enable clock controller driver in defconfig. Changes in v3: * rename clk_branch2_qca8k_ops to clk_branch2_mdio_ops. * fix review comments on yaml file. * use dev_err_probe on driver probe error. * only use the compatible "qcom,qca8084-nsscc". * remove enable clock controller driver patch. Changes in v4: * add _qcom_cc_really_probe function. * commonizing the probe function. * remove flag CLK_IS_CRITICAL from clocks only needed to be enabled in switch device. * update device tree property reg to 0x10. Luo Jie (4): clk: qcom: branch: Add clk_branch2_mdio_ops dt-bindings: clock: add qca8386/qca8084 clock and reset definitions clk: qcom: common: add _qcom_cc_really_probe clk: qcom: add clock controller driver for qca8386/qca8084 .../bindings/clock/qcom,qca8k-nsscc.yaml | 79 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-branch.c | 7 + drivers/clk/qcom/clk-branch.h | 1 + drivers/clk/qcom/common.c | 10 +- drivers/clk/qcom/common.h | 2 + drivers/clk/qcom/nsscc-qca8k.c | 2118 +++++++++++++++++ include/dt-bindings/clock/qcom,qca8k-nsscc.h | 101 + include/dt-bindings/reset/qcom,qca8k-nsscc.h | 75 + 10 files changed, 2400 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml create mode 100644 drivers/clk/qcom/nsscc-qca8k.c create mode 100644 include/dt-bindings/clock/qcom,qca8k-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,qca8k-nsscc.h base-commit: 479b322ee6feaff612285a0e7f22c022e8cd84eb