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Tue, 30 Jan 2024 23:07:50 -0800 (PST) Received: from [127.0.1.1] ([103.28.246.26]) by smtp.gmail.com with ESMTPSA id lp17-20020a056a003d5100b006ddd182bf1csm9087956pfb.46.2024.01.30.23.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 23:07:49 -0800 (PST) From: Manivannan Sadhasivam Subject: [PATCH v3 00/17] Fix Qcom UFS PHY clocks Date: Wed, 31 Jan 2024 12:37:23 +0530 Message-Id: <20240131-ufs-phy-clock-v3-0-58a49d2f4605@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAKvxuWUC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyjHUUlJIzE vPSU3UzU4B8JSMDIxMDQ2ND3dK0Yt2CjErd5Jz85Gxdc0tjyyRLI1OLJONkJaCegqLUtMwKsHn RsbW1AADUe1pfAAAA To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam , Conor Dooley , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3384; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=8oILixSlZ5urTs1vGCrQlsyLD+Svdi6zXRxdXJ11eVo=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlufG2op3Brs8QxQHR4Lma+anPdMoGprBMDMvoU 04otxHtgv+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbnxtgAKCRBVnxHm/pHO 9WobB/9NZYXT3tglVcat/alW1W2NsBvVeeQMIiTQSkS56WqIl4UHrc0WDixCWSWuq90DVYkkzQj DQR93pb3ofsHf4bPUZZv5CGNDYGZCKpMh/5OM+tGYjOElbgJKujYEIJjw50vJRw+7ZDXPKEV4be sFNBIU2jj44uXi7+XSbMAvTUX9Ho3lZ2OT4jV4lQMe0cHuUiZbidlw/QOQdhHrtO9tCuZtUlCov ZrxHspD4SpPtxp9deLDoG0fBe/cl8tIAIu2EYe0rxn6Mkg4HrbpK/dFVIHH3SB8XnuOGqrZuAyg MjZsL5Jw2TXxRS+wnDHx6CxtVTT7I95xGozCN6KUdmV+7jlP X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Hi, This series fixes the clocks supplied to QMP PHY IPs in the Qcom SoCs. All of the Qcom SoCs except MSM8996 require 3 clocks for QMP UFS: * ref - 19.2MHz reference clock from RPM/RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC or TCSR (TCSR since SM8550) MSM8996 only requires 'ref' and 'qref' clocks. Hence, this series fixes the binding, DT and GCC driver to reflect the actual clock topology. Note that the clock topology is not based on any downstream dts sources (even they are not accurate). But rather based on information from Qcom internal documentation and brain dump from Can Guo. Testing ======= Tested on Qualcomm RB5 development board based on SM8250 SoC. I don't expect this series to break other SoCs too. - Mani Changes in v3: * Added a patch for SM8650 * Collected review tags * Rebased on top of next/20231123 Changes in v2: * Reworded the commit message of patch 1 to justify ABI breakage * Collected review tags Signed-off-by: Manivannan Sadhasivam --- Manivannan Sadhasivam (17): dt-bindings: phy: qmp-ufs: Fix PHY clocks phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API dt-bindings: clock: qcom: Add missing UFS QREF clocks clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks arm64: dts: qcom: msm8996: Fix UFS PHY clocks arm64: dts: qcom: msm8998: Fix UFS PHY clocks arm64: dts: qcom: sdm845: Fix UFS PHY clocks arm64: dts: qcom: sm6115: Fix UFS PHY clocks arm64: dts: qcom: sm6125: Fix UFS PHY clocks arm64: dts: qcom: sm6350: Fix UFS PHY clocks arm64: dts: qcom: sm8150: Fix UFS PHY clocks arm64: dts: qcom: sm8250: Fix UFS PHY clocks arm64: dts: qcom: sc8180x: Fix UFS PHY clocks arm64: dts: qcom: sc8280xp: Fix UFS PHY clocks arm64: dts: qcom: sm8350: Fix UFS PHY clocks arm64: dts: qcom: sm8550: Fix UFS PHY clocks arm64: dts: qcom: sm8650: Fix UFS PHY clocks .../bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 48 ++++++++--------- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +- arch/arm64/boot/dts/qcom/msm8998.dtsi | 12 ++--- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 ++- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 ++++--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 +-- arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 ++- arch/arm64/boot/dts/qcom/sm6125.dtsi | 8 +-- arch/arm64/boot/dts/qcom/sm6350.dtsi | 8 +-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 8 +-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 +-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 +-- arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 ++-- arch/arm64/boot/dts/qcom/sm8650.dtsi | 8 +-- drivers/clk/qcom/gcc-sc8180x.c | 28 ++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 63 +++------------------- include/dt-bindings/clock/qcom,gcc-sc8180x.h | 2 + 17 files changed, 129 insertions(+), 125 deletions(-) --- base-commit: 06f658aadff0e483ee4f807b0b46c9e5cba62bfa change-id: 20240131-ufs-phy-clock-7939b9258b3c Best regards,