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Mon, 5 Feb 2024 16:22:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oltmanns.dev; s=MBO0001; t=1707146567; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=02ruNxK++PAViNf3AQJm4dGqBoNl7wJTiwKpbNLSczQ=; b=ZXjQNScEzCDO5NsBo6jCxc7YVO0UavM3fURJA02d2ggdkgyTOadBMCFAiGtdL0hSZM+XBb AvrfdmRiQ11Ft5QjNjBNDq+3/GuKmqGHuR4xpUR0fqvVgQfDPlxU+21lQON76gnN4fgChs 5/txjXryAkW91io2nbW80T03qpUXIgTiDDQnXDTKdOdrtEcxwjf1piZKGY33HeJP5Mq6np 4ZwEIXIN5T+Tvn1RfxJGdCLHzRJw1IbYiXlIFUY2bCVVBfnU44TaOG9+y9ecOlNy1/iVOW i4iPtDI/TDl4HC3mJFeHoLpoEGt6NxHM1XHpt1NKH8VZs6R1JUu9/gcf60VWdQ== From: Frank Oltmanns Subject: [PATCH v2 0/6] Pinephone video out fixes (flipping between two frames) Date: Mon, 05 Feb 2024 16:22:23 +0100 Message-Id: <20240205-pinephone-pll-fixes-v2-0-96a46a2d8c9b@oltmanns.dev> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; 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a=openpgp; fpr=02FD257B7F90E6B9A5444F969A69A208944AD3C7 On some pinephones the video output sometimes freezes (flips between two frames) [1]. It seems to be that the reason for this behaviour is that PLL-MIPI, PLL-GPU and GPU are operating outside their limits. In this patch series I propose the followin changes: 1. sunxi-ng: Adhere to the following constraints given in the Allwinner A64 Manual regarding PLL-MIPI: * M/N <= 3 * (PLL_VIDEO0)/M >= 24MHz * 500MHz <= clockrate <= 1400MHz 2. Choose a higher clock rate for the ST7703 based XDB599 panel, so that the panel function well with the Allwinner A64 SOC. PLL-MIPI must run between 500 MHz and 1.4 GHz. As PLL-MIPI runs at 6 times the panel's clock rate, we need the panel's clock to be at least 83.333 MHz. 3. Increase the minimum frequency in the A64 DTS OPPs from 120 MHz to 192 MHz. This further reduces the issue. Unfortunately, with these patches the issue [1] is not completely gone, but becomes less likely. Note, that when pinning the GPU to 432 MHz the issue completely disappears for me. I've searched the BSP and could not find any indication that supports the idea of having the three OPPs. The only frequency I found in the BPSs for A64 is 432 MHz, that has also proven stable for me. So, while increasing the minimum frequency to 192 MHz reduces the issue, should we maybe instead set the GPU to a fixed 432 MHz instead? I very much appreciate your feedback! [1] https://gitlab.com/postmarketOS/pmaports/-/issues/805 Signed-off-by: Frank Oltmanns --- Changes in v2: - dts: Increase minimum GPU frequency to 192 MHz. - nkm and a64: Add minimum and maximum rate for PLL-MIPI. - nkm: Use the same approach for skipping invalid rates in ccu_nkm_find_best() as in ccu_nkm_find_best_with_parent_adj(). - nkm: Improve names for ratio struct members and hence get rid of describing comments. - nkm and a64: Correct description in the commit messages: M/N <= 3 - Remove patches for nm as they were not needed. - st7703: Rework the commit message to cover more background for the change. - Link to v1: https://lore.kernel.org/r/20231218-pinephone-pll-fixes-v1-0-e238b6ed6dc1@oltmanns.dev --- Frank Oltmanns (6): clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate clk: sunxi-ng: nkm: Support minimum and maximum rate clk: sunxi-ng: a64: Set minimum and maximum rate for PLL-MIPI drm/panel: st7703: Drive XBD599 panel at higher clock rate arm64: dts: allwinner: a64: Fix minimum GPU OPP rate arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++-- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +++++++---- drivers/clk/sunxi-ng/ccu_nkm.c | 34 +++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_nkm.h | 4 ++++ drivers/gpu/drm/panel/panel-sitronix-st7703.c | 14 +++++------ 5 files changed, 56 insertions(+), 14 deletions(-) --- base-commit: 059c53e877ca6e723e10490c27c1487a63e66efe change-id: 20231218-pinephone-pll-fixes-0ccdfde273e4 Best regards,