| Message ID | 20240410033148.213991-1-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add notifier for PLL0 clock and set it 1.5GHz on | expand |
Quoting Xingyu Wu (2024-04-09 20:31:47) > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c > index 8f5e5abfa178..adf62e4d94e4 100644 > --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c > +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c > @@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, > } > EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); > > +/* > + * This clock notifier is called when the rate of PLL0 clock is to be change, s/change,/changed./ > + * The cpu_root clock should save curent parent clock and swicth its parent s/swicth/switch/ > + * clock to osc before PLL0 rate will be changed. And switch its parent clock > + * back after PLL rate finished.
On 10/04/2024 15:58, Stephen Boyd wrote: > > Quoting Xingyu Wu (2024-04-09 20:31:47) > > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c > > b/drivers/clk/starfive/clk-starfive-jh7110-sys.c > > index 8f5e5abfa178..adf62e4d94e4 100644 > > --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c > > +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c > > @@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct > > jh71x0_clk_priv *priv, } > > EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); > > > > +/* > > + * This clock notifier is called when the rate of PLL0 clock is to be > > +change, > > s/change,/changed./ Will fix. > > > + * The cpu_root clock should save curent parent clock and swicth its > > + parent > > s/swicth/switch/ Will fix. > > > + * clock to osc before PLL0 rate will be changed. And switch its > > + parent clock > > + * back after PLL rate finished. Thanks, Xingyu Wu
Hi Xingyu, On 10/04/2024 05:31, Xingyu Wu wrote: > This patch is to add the notifier for PLL0 clock and set the PLL0 rate > to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC. > > The first patch is to add the notifier for PLL0 clock. Setting the PLL0 > rate need the son clock (cpu_root) to switch its parent clock to OSC > clock and switch it back after setting PLL0 rate. It need to use the > cpu_root clock from SYSCRG and register the notifier in the SYSCRG > driver. > > The second patch is to set cpu_core rate to 500MHz and PLL0 rate to > 1.5GHz to fix the problem about the lower rate of CPUfreq on the > visionfive board. The cpu_core clock rate is set to 500MHz first to > ensure that the cpu frequency will not suddenly become high and the cpu > voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz. > The cpu voltage and frequency are then adjusted together by CPUfreq. > > Changes since v3: > - Added the notifier for PLL0 clock. > - Set cpu_core rate in DTS > > v3: https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivetech.com/ > > Changes since v2: > - Made the steps into the process into the process of setting PLL0 rate > > v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/ > > Changes since v1: > - Added the fixes tag in the commit. > > v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/ > > Xingyu Wu (2): > clk: starfive: jh7110-sys: Add notifier for PLL clock > riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by > setting PLL0 rate to 1.5GHz > > .../jh7110-starfive-visionfive-2.dtsi | 6 ++++ > .../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++++++++++++++++- > drivers/clk/starfive/clk-starfive-jh71x0.h | 2 ++ > 3 files changed, 38 insertions(+), 1 deletion(-) I only took a quick look so I'm not sure: does patch 2 depend on patch 1? In that case, I think the Fixes tag should be applied to both patches. And as this is a fix, will you respin a new version soon for 6.9? Thanks, Alex
On 25/04/2024 04:32, Alexandre Ghiti wrote: > > Hi Xingyu, > > On 10/04/2024 05:31, Xingyu Wu wrote: > > This patch is to add the notifier for PLL0 clock and set the PLL0 rate > > to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC. > > > > The first patch is to add the notifier for PLL0 clock. Setting the > > PLL0 rate need the son clock (cpu_root) to switch its parent clock to > > OSC clock and switch it back after setting PLL0 rate. It need to use > > the cpu_root clock from SYSCRG and register the notifier in the SYSCRG > > driver. > > > > The second patch is to set cpu_core rate to 500MHz and PLL0 rate to > > 1.5GHz to fix the problem about the lower rate of CPUfreq on the > > visionfive board. The cpu_core clock rate is set to 500MHz first to > > ensure that the cpu frequency will not suddenly become high and the > > cpu voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz. > > The cpu voltage and frequency are then adjusted together by CPUfreq. > > > > Changes since v3: > > - Added the notifier for PLL0 clock. > > - Set cpu_core rate in DTS > > > > v3: > > https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivet > > ech.com/ > > > > Changes since v2: > > - Made the steps into the process into the process of setting PLL0 > > rate > > > > v2: > > https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfive > > tech.com/ > > > > Changes since v1: > > - Added the fixes tag in the commit. > > > > v1: > > https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfive > > tech.com/ > > > > Xingyu Wu (2): > > clk: starfive: jh7110-sys: Add notifier for PLL clock > > riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by > > setting PLL0 rate to 1.5GHz > > > > .../jh7110-starfive-visionfive-2.dtsi | 6 ++++ > > .../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++++++++++++++++- > > drivers/clk/starfive/clk-starfive-jh71x0.h | 2 ++ > > 3 files changed, 38 insertions(+), 1 deletion(-) > > > I only took a quick look so I'm not sure: does patch 2 depend on patch 1? In that > case, I think the Fixes tag should be applied to both patches. Hi Alex, Yes, Patch 2 is dependent on patch 1. If patch 2 is applied alone, it does not work. I will add the Fixes tag both patches. > > And as this is a fix, will you respin a new version soon for 6.9? Yes. I will send a new version of this patches. Best regards, Xingyu Wu
This patch is to add the notifier for PLL0 clock and set the PLL0 rate to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC. The first patch is to add the notifier for PLL0 clock. Setting the PLL0 rate need the son clock (cpu_root) to switch its parent clock to OSC clock and switch it back after setting PLL0 rate. It need to use the cpu_root clock from SYSCRG and register the notifier in the SYSCRG driver. The second patch is to set cpu_core rate to 500MHz and PLL0 rate to 1.5GHz to fix the problem about the lower rate of CPUfreq on the visionfive board. The cpu_core clock rate is set to 500MHz first to ensure that the cpu frequency will not suddenly become high and the cpu voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz. The cpu voltage and frequency are then adjusted together by CPUfreq. Changes since v3: - Added the notifier for PLL0 clock. - Set cpu_core rate in DTS v3: https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivetech.com/ Changes since v2: - Made the steps into the process into the process of setting PLL0 rate v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/ Changes since v1: - Added the fixes tag in the commit. v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/ Xingyu Wu (2): clk: starfive: jh7110-sys: Add notifier for PLL clock riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz .../jh7110-starfive-visionfive-2.dtsi | 6 ++++ .../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++++++++++++++++- drivers/clk/starfive/clk-starfive-jh71x0.h | 2 ++ 3 files changed, 38 insertions(+), 1 deletion(-)