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The code additions are rather tiny: It only need some code in the Rockchip dw-mipi-dsi glue layer for this SoC and some changes in the clock driver. Support for the DPHY has already been added when the driver was initially submitted. I tested it with a 800x1280 DSI panel where all 4 lanes that are supported are used. Alex Bee (7): dt-bindings: display: rockchip,dw-mipi-dsi: Document RK3128 DSI dt-bindings: clock: rk3128: Add PCLK_MIPIPHY clk: rockchip: rk3128: Export PCLK_MIPIPHY clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks drm/rockchip: dsi: Add support for RK3128 ARM: dts: rockchip: Add DPHY for RK3128 ARM: dts: rockchip: Add DSI for RK3128 .../rockchip/rockchip,dw-mipi-dsi.yaml | 2 + arch/arm/boot/dts/rockchip/rk3128.dtsi | 49 +++++++++++++++++++ drivers/clk/rockchip/clk-rk3128.c | 3 +- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 ++++++++ include/dt-bindings/clock/rk3128-cru.h | 1 + 5 files changed, 74 insertions(+), 1 deletion(-)