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Tue, 28 May 2024 11:43:42 GMT Received: from hu-ajipan-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 28 May 2024 04:43:36 -0700 From: Ajit Pandey To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Vladimir Zapolskiy CC: , , , , Taniya Das , Jagadeesh Kona , Imran Shaik , Satya Priya Kakitapalli , Ajit Pandey Subject: [PATCH V3 0/8] clk: qcom: Add support for DISPCC, CAMCC and GPUCC on SM4450 Date: Tue, 28 May 2024 17:12:46 +0530 Message-ID: <20240528114254.3147988-1-quic_ajipan@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: EXb4yiK3u9kYrUGqZ8ivuKDZ_CKxBLZx X-Proofpoint-ORIG-GUID: EXb4yiK3u9kYrUGqZ8ivuKDZ_CKxBLZx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-28_07,2024-05-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1011 mlxscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2405280087 This patch series add dt-bindings, driver and device tree support for DISPCC, CAMCC and GPUCC on QCOM SM4450 platform and also includes a fix related to LUCID EVO PLL config issue in clk-alpha-pll driver which is required for correct scaling of few supported frequencies in graphics clock controllers on SM4450. Changes in V3: - [PATCH 1/8]: Updated commit tags order and added Reviewed-by: tags - [PATCH 3/8]: Fixed reusing of pll0_config and added Reviewed-by: tags - [PATCH 6/8]: Updated commit text and added Reviewed-by tags - [PATCH 8/8]: Updated node order for gpucc. - Link to v2: https://lore.kernel.org/all/20240416182005.75422-1-quic_ajipan@quicinc.com/ Ajit Pandey (8): clk: qcom: clk-alpha-pll: Fix CAL_L_VAL override for LUCID EVO PLL dt-bindings: clock: qcom: add DISPCC clocks on SM4450 clk: qcom: Add DISPCC driver support for SM4450 dt-bindings: clock: qcom: add CAMCC clocks on SM4450 clk: qcom: Add CAMCC driver support for SM4450 dt-bindings: clock: qcom: add GPUCC clocks on SM4450 clk: qcom: Add GPUCC driver support for SM4450 arm64: dts: qcom: sm4450: add camera, display and gpu clock controller .../bindings/clock/qcom,sm4450-camcc.yaml | 63 + .../bindings/clock/qcom,sm4450-dispcc.yaml | 71 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + arch/arm64/boot/dts/qcom/sm4450.dtsi | 38 + drivers/clk/qcom/Kconfig | 27 + drivers/clk/qcom/Makefile | 3 + drivers/clk/qcom/camcc-sm4450.c | 1688 +++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.c | 2 +- drivers/clk/qcom/dispcc-sm4450.c | 770 ++++++++ drivers/clk/qcom/gpucc-sm4450.c | 805 ++++++++ include/dt-bindings/clock/qcom,sm4450-camcc.h | 106 ++ .../dt-bindings/clock/qcom,sm4450-dispcc.h | 51 + include/dt-bindings/clock/qcom,sm4450-gpucc.h | 62 + 13 files changed, 3687 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm4450-camcc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml create mode 100644 drivers/clk/qcom/camcc-sm4450.c create mode 100644 drivers/clk/qcom/dispcc-sm4450.c create mode 100644 drivers/clk/qcom/gpucc-sm4450.c create mode 100644 include/dt-bindings/clock/qcom,sm4450-camcc.h create mode 100644 include/dt-bindings/clock/qcom,sm4450-dispcc.h create mode 100644 include/dt-bindings/clock/qcom,sm4450-gpucc.h