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Mon, 26 Aug 2024 08:04:38 +0000 Received: from NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn ([fe80::40dc:d70a:7a0b:3f92]) by NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn ([fe80::40dc:d70a:7a0b:3f92%5]) with mapi id 15.20.7897.021; Mon, 26 Aug 2024 08:04:38 +0000 From: Xingyu Wu To: Michael Turquette , Stephen Boyd , Conor Dooley , Emil Renner Berthing Cc: Hal Feng , Xingyu Wu , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v7 0/2] Add notifier for PLL0 clock and set it 1.5GHz on the JH7110 SoC Date: Mon, 26 Aug 2024 16:04:28 +0800 Message-Id: <20240826080430.179788-1-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: ZQ0PR01CA0013.CHNPR01.prod.partner.outlook.cn (10.2.0.72) To NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn (10.2.8.138) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: NTZPR01MB0956:EE_|NTZPR01MB1034:EE_ X-MS-Office365-Filtering-Correlation-Id: 1430e9cd-88c1-45e7-5ac0-08dcc5a5bb35 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|41320700013|52116014|1800799024|38350700014; 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The first patch is to add the notifier for PLL0 clock. Setting the PLL0 rate need the son clock (cpu_root) to switch its parent clock to OSC clock and switch it back after setting PLL0 rate. It need to use the cpu_root clock from SYSCRG and register the notifier in the SYSCRG driver. The second patch is to set cpu_core rate to 500MHz and PLL0 rate to 1.5GHz to fix the problem about the lower rate of CPUfreq on the visionfive board. The cpu_core clock rate is set to 500MHz first to ensure that the cpu frequency will not suddenly become high and the cpu voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz. The cpu voltage and frequency are then adjusted together by CPUfreq. According to some tests, U-Boot can also run 1.5G so that the DTS from kernel can be used on the U-Boot and could not cause any problems. So the way of patch v5 works. Changes since v6: - Used the patch 1 from v5 and added the reviewed tag. - Modified the patch 2 from v5 to fit the new jh7110-common.dtsi. v6: https://lore.kernel.org/all/20240603020607.25122-1-xingyu.wu@starfivetech.com/ Changes since v5: - Set the rate to 1.5G in the driver instead of DTS. v5: https://lore.kernel.org/all/20240507065319.274976-1-xingyu.wu@starfivetech.com/ Changes since v4: - Fixed the wrong words. - Added the Fixes tag in first patch. v4: https://lore.kernel.org/all/20240410033148.213991-1-xingyu.wu@starfivetech.com/ Changes since v3: - Added the notifier for PLL0 clock. - Set cpu_core rate in DTS v3: https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivetech.com/ Changes since v2: - Made the steps into the process into the process of setting PLL0 rate v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/ Changes since v1: - Added the fixes tag in the commit. v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/ Xingyu Wu (2): clk: starfive: jh7110-sys: Add notifier for PLL0 clock riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz .../boot/dts/starfive/jh7110-common.dtsi | 6 ++++ .../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++++++++++++++++- drivers/clk/starfive/clk-starfive-jh71x0.h | 2 ++ 3 files changed, 38 insertions(+), 1 deletion(-)