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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a86e548781csm446566b.28.2024.08.26.10.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 10:31:19 -0700 (PDT) From: Claudiu Beznea To: nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 0/3] clk: at91: sckc: Add macros for the slow clock Date: Mon, 26 Aug 2024 20:31:13 +0300 Message-Id: <20240826173116.3628337-1-claudiu.beznea@tuxon.dev> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi, Previously raw numbers were used for the clocks generated by the slow clock controller. This generated confusion and wrong IDs were used on device tree. To make it simpler and less error-prone series add IDs. Thank you, Claudiu Beznea Claudiu Beznea (3): dt-bindings: clk: at91: Add clock IDs for the slow clock controller clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks ARM: dts: microchip: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks arch/arm/boot/dts/microchip/sam9x60.dtsi | 18 +++++++++--------- arch/arm/boot/dts/microchip/sama7g5.dtsi | 16 ++++++++-------- drivers/clk/at91/sckc.c | 24 +++++++++++++----------- include/dt-bindings/clock/at91.h | 4 ++++ 4 files changed, 34 insertions(+), 28 deletions(-)